CY8C54 CYPRESS [Cypress Semiconductor], CY8C54 Datasheet - Page 29

• Manufacturer Part Number: CY8C54
• Description: Programmable System-on-Chip (PSoC)
• Manufacturer: CYPRESS [Cypress Semiconductor]

6.4.1 Drive Modes
Each GPIO and SIO pin is individually configurable into one of
the eight drive modes listed in
are used for each pin (DM[2:0]) and set in the PRTxDM[2:0]
registers.
of the eight drive modes.
based on the port data register value or digital array signal if
Table 6-6. Drive Modes
Document Number: 001-55036 Rev. *A
High Impedance Analog
The default reset state with both the output driver and digital
input buffer turned off. This prevents any current from flowing
in the I/O’s digital input buffer due to a floating voltage. This
state is recommended for pins that are floating or that support
an analog voltage. High impedance analog pins do not provide
digital input functionality.
To achieve the lowest chip current in sleep modes, all I/Os
must either be configured to the high impedance analog mode,
Diagram
0
1
2
3
4
5
6
7
Figure 6-9
High impedence analog
High Impedance digital
Resistive pull up
Resistive pull down
Open drain, drives low
Open drain, drive high
Strong drive
Resistive pull up and pull down
depicts a simplified pin view based on each
Table 6-6
Drive Mode
Table
0.
4.
DR
PS
DR
PS
shows the I/O pin’s drive state
Analog
Open Drain ,
Drives Low
High Impedance
6-6. Three configuration bits
PRELIMINARY
Pin
Pin
1.
5.
DR
PS
DR
PS
Digital
PRTxDM2
Figure 6-9. Drive Mode
Open Drain ,
Drives High
High Impedance
0
0
0
0
1
1
1
1
Vio
Pin
Pin
PRTxDM1
bypass mode is selected. Note that the actual I/O pin voltage is
determined by a combination of the selected drive mode and the
load at the pin. For example, if a GPIO pin is configured for
resistive pull up mode and driven high while the pin is floating,
the voltage measured at the pin is a high logic state. If the same
GPIO pin is externally tied to ground then the voltage unmea-
sured at the pin is a low logic state.
2.
6.
DR
PS
DR
PS
or have their pins driven to a power supply rail by the PSoC
device or by external circuitry.
High Impedance Digital
The input buffer is enabled for digital signal input. This is the
standard high impedance (HiZ) state recommended for digital
inputs.
Resistive Pull Up or Resistive Pull Down
Resistive pull up or pull down, respectively, provides a series
resistance in one of the data states and strong drive in the
Pull Up
0
0
1
1
0
0
1
1
Resistive
Strong Drive
PSoC
Vio
Vio
®
PRTxDM0
Pin
Pin
5: CY8C54 Family Data Sheet
0
1
0
1
0
1
0
1
PS
3.
7.
DR
DR
PS
Resistive
Pull Up and Down
Resistive
Pull Down
Res High (5K)
Res High (5K)
Vio
Vio
PRTxDR = 1
Strong High
Strong High
Strong High
High-Z
High-Z
High-Z
Pin
Pin
Res Low (5K)
Res Low (5K)
PRTxDR = 0
Strong Low
Strong Low
Strong Low
High-Z
High-Z
High-Z
Page 29 of 93
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