USB3450-FZG SMSC [SMSC Corporation], USB3450-FZG Datasheet
USB3450-FZG
Related parts for USB3450-FZG
USB3450-FZG Summary of contents
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... Max) Internal 1.8 volt regulators allow operation from a ■ single 3.3 volt supply Internal short circuit protection of DP and DM lines to ■ VBUS or ground. SMSC USB3450 USB3450 Hi-Speed USB Host or Device PHY With UTMI+ Interface Integrated 24MHz Crystal Oscillator supports either ■ crystal operation or 24MHz external clock input. ...
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... ORDER NUMBER(S): USB3450-FZG FOR 40 PIN, QFN PACKAGE (GREEN, LEAD-FREE) 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Copyright © 2005 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given ...
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... Hi-Speed USB Host or Device PHY With UTMI+ Interface Datasheet 0.1 Reference Documents Universal Serial Bus Specification, Revision 2.0, April 27, 2000 ■ Hi-Speed Transceiver Macrocell Interface (UTMI) Specification, Version 1.02, May 27, 2000 ■ UTMI+ Specification, Revision 1.0, February 2, 2004 ■ SMSC USB3450 3 DATASHEET Revision 0.1 (05-11-05) ...
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... Table of Contents 0.1 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chapter 3 Pin Configuration and Pin Definitions 3.1 USB3450 Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Pin Definitions Chapter 4 Limiting Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chapter 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Chapter 6 Detailed Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 8bit Bi-Directional Data Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 TX Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 RX Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 ...
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... Figure 7.5 HS Detection Handshake Timing Behavior (HS Mode Figure 7.6 HS Detection Handshake Timing Behavior from Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 7.7 Resume Timing Behavior (HS Mode Figure 7.8 Device Attach Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 7.9 USB3450 Application Diagram (Top View Figure 8.1 USB3450-FZG 40 Pin QFN Package Outline 0.9 mm Body (Lead Free SMSC USB3450 5 DATASHEET Revision 0.1 (05-11-05) ...
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... List of Tables Table 3.1 USB3450 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 4.1 Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4.3 Recommended External Clock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5.1 Electrical Characteristics: Supply Pins Table 5.2 Electrical Characteristics: CLKOUT Start- Table 5.3 DC Electrical Characteristics: Logic Pins Table 5.4 DC Electrical Characteristics: Analog I/O Pins (DP/DM Table 5.5 Dynamic Characteristics: Analog I/O Pins (DP/DM Table 5 ...
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... UTMI+ USB App. Link Figure 1.1 Basic UTMI+ USB Device Block Diagram The USB3450 provides a fully compliant Hi-Speed interface, and supports Hi-Speed (HS), Full-Speed (FS), and Low-Speed (LS) USB. The USB3450 supports all levels of the UTMI+ specification as shown in Figure 1.2. Hi-Speed Peripheral, host controllers, On- (HS, FS, LS, preamble packet) ...
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... Applications The USB3450 is targeted for any application where a high speed USB connection is desired. The USB3450 is well suited for: Cell Phones ■ MP3 Players ■ Scanners ■ Set Top Boxes ■ Printers ■ External Hard Drives ■ Still and Video Cameras ■ ...
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... Hi-Speed USB Host or Device PHY With UTMI+ Interface Datasheet Chapter 2 Functional Overview The USB3450 is a highly integrated USB transceiver system. It contains a complete Hi-Speed PHY with the UTMI+ industry standard interface to support fast time to market for a USB controller. The USB3450 is composed of the functional blocks shown in Internal VDD3 ...
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... Chapter 3 Pin Configuration and Pin Definitions The USB3450 is offered pin QFN package. The pin definitions and locations are documented below. 3.1 USB3450 Pin Locations XCVRSEL0 1 TERMSEL 2 TXREADY 3 SUSPENDN 4 TXVALID 5 RESET 6 VDD3 Figure 3.1 USB3450 Pinout - Top View The flag of the QFN package must be connected to ground. ...
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... SUSPENDN 5 TXVALID 6 RESET 7 VDD3 VDD3.3 SMSC USB3450 Table 3.1 USB3450 Pin Definitions ACTIVE TYPE LEVEL DESCRIPTION Input N/A Transceiver Select. These signals select between the FS and HS transceivers: Transceiver select. 00: HS 01: FS 10: LS 11: LS data, FS rise/fall times Input N/A Termination Select. This signal selects between the ...
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... Table 3.1 USB3450 Pin Definitions (continued) DIRECTION, PIN NAME 12 XCVRSEL[1] 13 RXACTIVE 14 OPMODE[1] 15 OPMODE[0] 16 CLKOUT 17 LINESTATE[1] 18 LINESTATE[0] 19 VDD1.8 20 VDD3.3 21 HOSTDISC Revision 0.1 (05-11-05) Hi-Speed USB Host or Device PHY With UTMI+ Interface ACTIVE TYPE LEVEL DESCRIPTION Input N/A Transceiver Select. These signals select between the FS and HS transceivers: Transceiver select ...
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... Hi-Speed USB Host or Device PHY With UTMI+ Interface Datasheet Table 3.1 USB3450 Pin Definitions (continued) DIRECTION, PIN NAME 22 DATA[7] 23 DATA[6] 24 DATA[5] 25 DATA[4] 26 DATA[3] 27 DATA[2] 28 DATA[1] 29 DATA[0] 30 RXVALID 31 HOST 32 RXERROR 33 VDD3.3 34 VDD1 SMSC USB3450 ACTIVE TYPE LEVEL DESCRIPTION I/O, N/A 8-bit bi-directional data bus. Data[7] is the MSB and Data[0] is the LSB ...
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... Table 3.1 USB3450 Pin Definitions (continued) DIRECTION, PIN NAME VDDA1.8 38 VDD3.3 39 VDD3.3 40 RBIAS GND FLAG Revision 0.1 (05-11-05) Hi-Speed USB Host or Device PHY With UTMI+ Interface ACTIVE TYPE LEVEL DESCRIPTION Input, N/A Crystal pin. A 24MHz crystal is supported. The crystal is placed across XI and XO. An external ...
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... V DD3.3 Input Voltage on Digital Pins V I Input Voltage on Analog I/O V I(I/O) Pins (DP, DM) Ambient Temperature T A Table 4.3 Recommended External Clock Conditions PARAMETER SYMBOL System Clock Frequency System Clock Duty Cycle SMSC USB3450 CONDITIONS MIN -0.5 -0.5 -0.5 -0.5 0 -55 CONDITIONS MIN 3.0 0.0 0.0 0 CONDITIONS MIN XI driven by the external clock; ...
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... CONDITIONS MIN CONDITIONS MIN 8mA -8mA V OH DD3.3 - 0 +70C; unless otherwise specified DATASHEET Datasheet (Note 5.1) TYP MAX UNITS 60.5 mA 57.5 mA 60.6 mA 62 TYP MAX UNITS 2.25 3.5 ms TYP MAX UNITS 0 DD3.3 0 ± SMSC USB3450 ...
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... Mode Voltage Range HS Squelch Detection Threshold (Differential) V HSSQ Output Levels Hi-Speed Low Level V HSOL Output Voltage (DP/DM referenced to GND) Hi-Speed High Level V HSOH Output Voltage (DP/DM referenced to GND) SMSC USB3450 CONDITIONS MIN | V(DP) - V(DM) | 0.2 0.8 2.0 0.050 Pull-up resistor on DP 1.5kΩ DD3.3 Pull-down resistor on DP, 2.8 DM; ...
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... Hi-Speed specification Eye pattern of Template 4 in Hi-Speed specification Eye pattern of Template 4 in Hi-Speed specification = 0V +70C; unless otherwise specified DATASHEET Datasheet TYP MAX UNITS 10 mV 1100 mV -500 mV ± TYP MAX UNITS 2.0 V 111 SMSC USB3450 ...
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... Datasheet PARAMETER SYMBOL V V DDA1.8 DDA1 DDA1.8 DDA1 DD1.8 DD1.8 Note 3.0 to 3.6V; V DD3.3 SMSC USB3450 Table 5.6 Regulator Output Voltages CONDITIONS Normal Operation (SUSPENDN = 1) Low Power mode (SUSPENDN = +70C; unless otherwise specified DATASHEET MIN TYP MAX UNITS 1.6 1 ...
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... The XCVRSELECT signal determines whether the timing relationship is applied to the data and control signals. Figure 6.2 FS CLK Relationship to Receive Data and Control Signals Revision 0.1 (05-11-05) Hi-Speed USB Host or Device PHY With UTMI+ Interface shows the functional block diagram of the USB3450. Each of the functions is 20 DATASHEET Datasheet Figure 6.2 ...
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... After the Link asserts TXVALID it can assume that the transmission has started when it detects ■ TXREADY has been asserted. The Link must assume that the USB3450 has consumed a data byte if TXREADY and TXVALID ■ are asserted on the rising edge of CLKOUT. The Link must have valid packet information (PID) asserted on the DATA bus coincident with the ■ ...
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... Each time 8 stuffed bits are accumulated the USB3450 will negate RXVALID for one clock cycle, thus skipping a byte time. When the EOP is detected the USB3450 will negate RXACTIVE and RXVALID. After the EOP has been stripped the USB3450 will begin looking for the next packet. ...
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... Hi-Speed USB Host or Device PHY With UTMI+ Interface Datasheet Figure 6.5 Receive Timing for a Handshake Packet (no CRC) Figure 6.6 Receive Timing for Setup Packet SMSC USB3450 23 DATASHEET Revision 0.1 (05-11-05) ...
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... Termination Resistors The USB3450 transceiver fully integrates all of the USB termination resistors. The USB3450 includes two 1.5kΩ pull-up resistors on DP and DM and a 15kΩ pull-down resistor on both DP and DM. In addition the 45Ω high speed termination resistors are also integrated. These integrated resistors require no tuning or trimming by the Link ...
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... Host HS/FS Resume Host low Speed Host LS Suspend Host LS Resume Host Test J/Test_K Peripheral Settings Peripheral Chirp Peripheral HS Peripheral FS Peripheral HS/FS Suspend Peripheral HS/FS Resume Peripheral LS Peripheral LS Suspend Peripheral LS Resume Peripheral Test J/Test K SMSC USB3450 UTMI+ INTERFACE SETTINGS XXb Xb 01b Xb 0b 01b 0b 00b 1b 0b 00b 0b ...
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... The USB3450 uses an internal crystal driver and PLL sub-system to provide a clean 480MHz reference clock that is used by the PHY during both transmit and receive. The USB3450 requires a clean 24MHz crystal or clock as a frequency reference. If the 24MHz reference is noisy or off frequency the PHY may not operate correctly ...
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... There is not a concept of variable single-ended thresholds in the Hi-Speed specification for HS mode. The HS receiver is used to detect Chirp where the output of the HS receiver is always qualified with the Squelch signal. If squelched, the output of the HS receiver is ignored. In the USB3450 alternative to using variable thresholds for the single-ended receivers, the following approach is used. LINESTATE[1:0] ...
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... The only exception to this is when OPMODE[1:0] is set to state 2 while TXVALID has been asserted (the transceiver is transmitting a packet), in order to flag a transmission error. In this case, the USB3450 has already transmitted the SYNC pattern so upon negation of TXVALID the EOP must also be transmitted to properly terminate the packet. Changing the OPMODE[1:0] signals under all other conditions, while the transceiver is transmitting or receiving data will generate undefined results ...
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... Link must then check LINESTATE for the J condition asserted at time T2, then the upstream port is asserting a soft SE0 and the USB state indicating a suspend condition. By time T4 the device must be fully suspended. SMSC USB3450 DESCRIPTION 0 (reference) HS Reset 0ms < T1 < HS Reset T0 + 3.125ms T1 + 100µ ...
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... Revision 0.1 (05-11-05) Hi-Speed USB Host or Device PHY With UTMI+ Interface DESCRIPTION 0 (reference) HS Reset 0ms < T1 < HS Reset T0 + 3.125ms T1 + 100 µs < T2 < 875µs HS Reset T0 + 5ms HS Reset T0 + 10ms 30 DATASHEET Datasheet VALUE SMSC USB3450 ...
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... This transceiver design pushes as much of the responsibility for timing events on to the Link as possible, and the Link requires a stable CLKOUT signal to perform accurate timing. In case 2 and 3 above, CLKOUT has been running and is stable, however in case 1 the USB3450 is reset from a suspend state, and the internal oscillator and clocks of the transceiver are assumed to be powered down ...
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... The Link must assert the Chirp K for 66000 CLKOUT cycles to ensure a 1ms minimum duration. ■ Revision 0.1 (05-11-05) Hi-Speed USB Host or Device PHY With UTMI+ Interface DESCRIPTION 0 (reference) T0 < T1 < HS Reset T0 + 6.0ms T1 + 1.0 ms < T2 < HS Reset T0 + 7.0ms T2 < T3 < T2+100µ 1.0ms < T4 < 2.5ms HS Reset T0 + 10ms 32 DATASHEET Datasheet VALUE SMSC USB3450 ...
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... LINESTATE = J State. The Link must employ a counter (Chirp Count) to count the number of Chirp K and Chirp J states. Note that LINESTATE does not filter the bus signals so the requirement that a bus state must be “continuously asserted for 2.5µs” must be verified by the Link sampling the LINESTATE signals. SMSC USB3450 !K K State Detect K? ...
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... Datasheet VALUE 0 (reference) T0 < T1 < HS Reset T0 + 6.0ms T0 + 1.0ms < T2 < HS Reset T0 + 7.0ms T2 < T3 < T2+100µ 40µs < T4 < 60µ 40µs < T5 < 60µ < T7 < 500µ 500µs < T8 < 100µs HS Reset T0 + 10ms SMSC USB3450 ...
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... OPMODE 0 OPMODE 1 XCVRSELECT TERMSELECT SUSPENDN TXVALID CLK60 DP/DM J Figure 7.6 HS Detection Handshake Timing Behavior from Suspend SMSC USB3450 Figure 7.6 shows how CLKOUT is used to control the duration of the for completion of the High Speed Handshake SE0 CLK power up time Device Chirp K 35 DATASHEET Section 7.9, " ...
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... TXVALID asserted, and all 0's data is presented on the DATA bus for at least 1ms (T1 - T2). Revision 0.1 (05-11-05) Hi-Speed USB Host or Device PHY With UTMI+ Interface DESCRIPTION 36 DATASHEET Datasheet }, the Link must see FILT VALUE 0 (HS Reset T0) T0 < T1 < 5.6ms T1 < T2 < 5.8ms T2 + 1.0 ms < T3 < 7 < T3 < 20.0ms SMSC USB3450 ...
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... Link implementations key off the 'J' to 'K' transition for exiting suspend mode (SUSPENDN = 1). And within 1.25µs after the transition to the SE0 state (low-speed EOP) the Link must enable normal operation, i.e. enter mode depending on the mode the device was in when it was suspended. SMSC USB3450 DESCRIPTION 0 (reference) T0 < T1 < 10ms. ...
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... HS Device Attach Figure 7.8 demonstrates the timing of the USB3450 control signals during a device attach event. When a HS device is attached to an upstream port, power is asserted to the device and the device sets XCVRSELECT and TERMSELECT to FS mode (time T1 the +5V power available on the USB cable. Device Reset in BUS within normal operational range as defined in the Hi-Speed specification ...
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... USB ID Connector (Standard DP or Mini Min Max VBUS Host 100uF Device 1uF 10uF OTG Device 1uF 6.5uF Figure 7.9 USB3450 Application Diagram (Top View) SMSC USB3450 1 TERMSEL 2 TXREADY 3 4 USB3450 TXVALID Hi-Speed USB 5 RESET UTMI+ PHY 6 40 Pin QFN VDD3 ...
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... MAXIMUM MATERIAL CONDITION. DIMENSIONS "b" APPLIES TO PLATED TERMINALS AND IT IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE TERMINAL TIP. 3. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE AREA INDICATED. Figure 8.1 USB3450-FZG 40 Pin QFN Package Outline 0.9 mm Body (Lead Free) D2 TERMINAL #1 e ...