FDC37C669_07 SMSC [SMSC Corporation], FDC37C669_07 Datasheet - Page 106

• Manufacturer Part Number: FDC37C669_07
• Description: PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support
• Manufacturer: SMSC [SMSC Corporation]

are always possible with standard or PS/2 mode
using program control of the control signals.
Interrupts
The interrupts are enabled by serviceIntr in the
ecr register.
serviceIntr = 1
serviceIntr = 0
The interrupt generated is ISA friendly in that it
must pulse the interrupt line low, allowing for
interrupt sharing. After a brief pulse low
following the interrupt event, the interrupt line is
tri-stated so that other interrupts may assert.
An interrupt is generated when:
1. For DMA transfers: When serviceIntr is 0,
2. For Programmed I/O:
dmaEn is 1 and the DMA TC is received.
a.
When serviceIntr is 0, dmaEn is 0,
direction
writeIntrThreshold or more free bytes in
the FIFO.
generated when serviceIntr is cleared
to
writeIntrThreshold or more free bytes in
the FIFO.
0
Disables the DMA and all of
the service interrupts.
Enables the selected interrupt
condition.
condition is valid, then the
interrupt
immediately when this bit is
changed from a 1 to a 0. This
can occur during Programmed
I/O if the number of bytes
removed or added from/to the
FIFO does not cross the
threshold.
is
whenever
Also, an interrupt is
0
and
If the interrupting
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106
3. When nErrIntrEn is 0 and nFault transitions
4. When ackIntEn is 1 and the nAck signal
FIFO Operation
The
configuration registers. All data transfers to or
from the parallel port can proceed in DMA or
Programmed I/O (non-DMA) mode as indicated
by the selected mode.
selecting the Parallel Port FIFO mode or ECP
Parallel Port Mode. (FIFO test mode will be
addressed separately). After a reset, the FIFO
is disabled. Each data byte is transferred by a
Programmed I/O cycle or PDRQ depending on
the selection of DMA or Programmed I/O mode.
The following paragraphs detail the operation of
the FIFO flow control.
<threshold> ranges from 1 to 16.
parameter FIFOTHR, which the user programs,
is one less and ranges from 0 to 15.
A low threshold value (i.e. 2) results in longer
periods of time between service requests, but
requires faster servicing of the request for both
read and write cases. The host must be very
responsive to the service request. This is the
desired case for use with a "fast" system.
b.
from high to low or when nErrIntrEn is set
from 1 to 0 and nFault is asserted.
transitions from a low to a high.
FIFO
(1)
threshold
When serviceIntr is 0, dmaEn
is 0, direction is 1 and there
are readIntrThreshold or more
bytes in the FIFO.
interrupt is generated when
serviceIntr is cleared to 0
whenever
readIntrThreshold
bytes in the FIFO.
is
The FIFO is used by
In these descriptions,
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