FDC37C669_07 SMSC [SMSC Corporation], FDC37C669_07 Datasheet - Page 92

• Manufacturer Part Number: FDC37C669_07
• Description: PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support
• Manufacturer: SMSC [SMSC Corporation]

The EPP Data Port 3 is located at an offset of
'07H' from the base address.
DATA PORT 0 for a description of operation.
This register is only available in EPP mode.
EPP 1.9 OPERATION
When the EPP mode is selected in the
configuration register, the standard and bi-
directional modes are also available. If no EPP
Read, Write or Address cycle is currently
executing, then the PDx bus is in the standard or
bi-directional mode, and all output signals
(STROBE, AUTOFD, INIT) are as set by the
SPP Control Port and direction is controlled by
PCD of the Control port.
In EPP mode, the system timing is closely
coupled to the EPP timing. For this reason, a
watchdog timer is required to prevent system
lockup. The timer indicates if more than 10usec
have elapsed from the start of the EPP cycle
(nIOR or nIOW asserted) to nWAIT being
deasserted (after command).
occurs, the current EPP cycle is aborted and the
time-out condition is indicated in Status bit 0.
During an EPP cycle, if STROBE is active, it
overrides the EPP write signal forcing the PDx
bus to always be in a write mode and the
nWRITE signal to always be asserted.
Software Constraints
Before an EPP cycle is executed, the software
must ensure that the control register bit PCD is
a logic "0" (i.e. a 04H or 05H should be written
to the Control port). If the user leaves PCD as a
logic "1", and attempts to perform an EPP write,
the chip is unable to perform the write (because
PCD is a logic "1") and will appear to perform an
EPP read on the parallel bus, no error is
indicated.
EPP 1.9 Write
The timing for a write operation (address or
Refer to EPP
If a time-out
92
data) is shown in timing diagram EPP 1.9 Write
Data or Address cycle.
active low at the start of each EPP write and is
released when it has been determined that the
write cycle can complete.
complete under the following circumstances:
1.
2.
Write Sequence of operation
1.
2.
3.
4.
5.
6.
7.
If the EPP bus is not ready (nWAIT is active
low) when nDATASTB or nADDRSTB goes
active then the write can complete when
nWAIT goes inactive high.
If the EPP bus is ready (nWAIT is inactive
high) then the chip must wait for it to go
active low before changing the state of
nDATASTB, nWRITE or nADDRSTB.
write
determined inactive.
The host selects an EPP register, places
data on the SData bus and drives nIOW
active.
The chip drives IOCHRDY inactive (low).
If WAIT is not asserted, the chip must wait
until WAIT is asserted.
The chip places address or data on PData
bus, clears PDIR, and asserts nWRITE.
Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus contains valid
information, and the WRITE signal is valid.
Peripheral deasserts nWAIT,
that any setup requirements have been
satisfied and the chip may begin the
termination phase of the cycle.
a)
b)
The chip deasserts nDATASTB
nADDRSTRB,
beginning of the termination phase. If
it has not already done so, the
peripheral should latch the information
byte now.
The chip latches the data from the
SData bus for the PData bus and
asserts (releases) IOCHRDY allowing
the
cycle.
can
host to complete the write
complete
this
IOCHRDY is driven
The write cycle can
once
marks
nWAIT
indicating
The
the
or
is