MFRC52201HN1/TRAYB NXP [NXP Semiconductors], MFRC52201HN1/TRAYB Datasheet
MFRC52201HN1/TRAYB
Related parts for MFRC52201HN1/TRAYB
MFRC52201HN1/TRAYB Summary of contents
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MFRC522 Contactless reader IC Rev. 3.3 — 26 October 2009 112133 1. Introduction This document describes the functionality and electrical specifications of the contactless reader/writer MFRC522. 2. General description The MFRC522 is a highly integrated reader/writer IC for contactless communication ...
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NXP Semiconductors N SPI Mbit RS232 Serial UART up to 1228.8 kBd, with voltage levels dependant on pin voltage supply I FIFO buffer handles 64 byte send and receive I Flexible interrupt modes I ...
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... Type number Package Name [1] MFRC52201HN1/TRAYB HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; [2] MFRC52201HN1/TRAYBM HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; [1] Delivered in one tray. [2] Delivered in five trays. 6. Block diagram The analog interface handles the modulation and demodulation of the analog signals. ...
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NXP Semiconductors SDA/NSS/RX EA I2C D1/ADR_5 SPI, UART, I FIFO CONTROL 64-BYTE FIFO BUFFER CONTROL REGISTER BANK MIFARE CLASSIC UNIT RANDOM NUMBER GENERATOR AMPLITUDE RATING REFERENCE VOLTAGE ANALOG TEST I-CHANNEL MULTIPLEXOR AMPLIFIER AND DIGITAL TO I-CHANNEL ANALOG ...
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NXP Semiconductors 7. Pinning information Fig 3. 7.1 Pin description Table 3. Pin description [1] Pin Symbol Type 1 I2C I 2 PVDD P 3 DVDD P 4 DVSS G 5 PVSS G 6 NRSTPD I 7 MFIN I 8 ...
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NXP Semiconductors Table 3. Pin description …continued [1] Pin Symbol Type 16 VMID AVSS G 19 AUX1 O 20 AUX2 O 21 OSCIN I 22 OSCOUT O 23 IRQ O 24 SDA I/O NSS I ...
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NXP Semiconductors 8. Functional description The MFRC522 transmission module supports the Read/Write mode for ISO/IEC 14443 A/MIFARE using various transfer speeds and modulation protocols. Fig 4. The physical level communication is shown in (1) Reader to card 100 % ASK, ...
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NXP Semiconductors ISO/IEC 14443 A framing at 106 kBd start start bit is 1 ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd start start bit is 0 burst of 32 subcarrier clocks Fig 6. Data coding ...
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NXP Semiconductors 8.1.2 Serial Peripheral Interface A serial peripheral interface (SPI compatible) is supported to enable high-speed communication to the host. The interface can handle data speeds Mbit/s. When communicating with a host, the MFRC522 acts as ...
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NXP Semiconductors 8.1.2.2 SPI write data To write data to the MFRC522 using SPI requires the byte order shown in possible to write data bytes by only sending one address byte. The first send byte defines both ...
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NXP Semiconductors 8.1.3.2 Selectable UART transfer speeds The internal UART interface is compatible with an RS232 serial interface. The default transfer speed is 9.6 kBd. To change the transfer speed, the host controller must write a value for the new ...
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NXP Semiconductors 8.1.3.3 UART framing Table 11. Bit Start Data Stop Remark: The LSB for data and address bytes must be sent first. No parity bit is used during transmission. Read data: To read data using the UART interface, the ...
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NXP Semiconductors Table 13. Pin RX (pin 24) TX (pin 31) MFRC522_33 Product data sheet PUBLIC Write data byte order Byte 0 address 0 - Rev. 3 — 26 October 2009 112133 MFRC522 Contactless reader IC Byte 1 data 0 ...
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ADDRESS ( DTRQ (1) Reserved. Fig 10. UART write data timing diagram Remark: The data byte can be sent directly after the address byte on pin RX. Address byte: The ...
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NXP Semiconductors Table 14. 7 (MSB read 0 = write 2 8.1.4 I C-bus interface C-bus (Inter-IC) interface is supported to enable a low-cost, low pin count serial bus interface to the host. The I ...
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NXP Semiconductors 8.1.4.1 Data validity Data on the SDA line must be stable during the HIGH clock period. The HIGH or LOW state of the data line must only change when the clock signal on SCL is LOW. Fig 12. ...
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NXP Semiconductors 8.1.4.4 Acknowledge An acknowledge must be sent at the end of one data byte. The acknowledge-related clock pulse is generated by the master. The transmitter of data, either master or slave, releases the SDA line (HIGH) during the ...
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NXP Semiconductors 8.1.4.5 7-Bit addressing During the I determine which slave will be selected by the master. Several address numbers are reserved. During device configuration, the designer must ensure that collisions with these reserved addresses cannot occur. Check the I ...
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NXP Semiconductors 8.1.4.7 Register read access To read out data from a specific register address in the MFRC522, the host controller must use the following procedure: • Firstly, a write access to the specific register address must be performed as ...
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NXP Semiconductors 8.1.4.8 High-speed mode In High-speed mode (HS mode), the device can transfer information at data rates 3.4 Mbit/s, while remaining fully downward-compatible with Fast or Standard mode (F/S mode) for bidirectional communication in a mixed-speed ...
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NXP Semiconductors S SDA high SCL high Sr SDA high SCL high Master current source pull-up = Resistor pull-up 2 Fig 19. I C-bus HS mode protocol frame MFRC522_33 Product data sheet PUBLIC 8-bit master code ...
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NXP Semiconductors 8.1.4.11 Switching between F/S mode and HS mode After reset and initialization, the MFRC522 is in Fast mode (which is in effect F/S mode as Fast mode is downward-compatible with Standard mode). The connected MFRC522 recognizes the “S ...
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NXP Semiconductors 8.2 Analog interface and contactless UART 8.2.1 General The integrated contactless UART supports the external host online with framing and error checking of the protocol requirements up to 848 kBd. An external circuit can be connected to the ...
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NXP Semiconductors Table 16. Register and bit settings controlling the signal on pin TX2 Bit Bit Bit Tx1RFEn Force Tx2CW 100ASK [ not care. The ...
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NXP Semiconductors 8.2.3 Serial data switch Two main blocks are implemented in the MFRC522. The digital block comprises the state machines, encoder/decoder logic. The analog block comprises the modulator and antenna drivers, the receiver and amplifiers possible for ...
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Remark: Pins MFIN and MFOUT have a dedicated supply on pin SVDD with the ground on pin PVSS. If pin MFIN is not used it must be connected to either pin SVDD or pin PVSS. If pin SVDD is not ...
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NXP Semiconductors 8.2.5 CRC coprocessor The following CRC coprocessor parameters can be configured: • The CRC preset value can be either 0000h, 6363h, A671h or FFFFh depending on the ModeReg register’s CRCPreset[1:0] bits setting • The CRC polynomial for the ...
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NXP Semiconductors • FIFO buffer almost empty warning: Status1Reg register’s LoAlert bit • FIFO buffer overflow warning: ErrorReg register’s BufferOvfl bit. The BufferOvfl bit can only be cleared by setting the FIFOLevelReg register’s FlushBuffer bit. The MFRC522 can generate an ...
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NXP Semiconductors The ComIrqReg register’s ErrIRq bit indicates an error detected by the contactless UART during send or receive. This is indicated when any bit is set to logic 1 in register ErrorReg. Table 18. Interrupt flag TimerIRq TxIRq CRCIRq ...
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NXP Semiconductors The timer can be started manually using the ControlReg register’s TStartNow bit and stopped using the ControlReg register’s TStopNow bit. The timer can also be activated automatically to meet any dedicated protocol requirements, by setting the TModeReg register’s ...
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NXP Semiconductors 8.6 Power reduction modes 8.6.1 Hard power-down Hard power-down is enabled when pin NRSTPD is LOW. This turns off all internal current sinks including the oscillator. All digital input buffers are separated from the input pins and clamped ...
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NXP Semiconductors The clock applied to the MFRC522 provides a time basis for the synchronous system’s encoder and decoder. The stability of the clock frequency, therefore important factor for correct operation. To obtain optimum performance, clock jitter must ...
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NXP Semiconductors 9. MFRC522 registers 9.1 Register bit behavior Depending on the functionality of a register, the access conditions to the register can vary. In principle, bits with same behavior are grouped in common registers. The access conditions are described ...
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NXP Semiconductors 9.2 Register overview Table 20. MFRC522 register overview Address Register name (hex) Page 0: Command and status 00h Reserved 01h CommandReg 02h ComlEnReg 03h DivlEnReg 04h ComIrqReg 05h DivIrqReg 06h ErrorReg 07h Status1Reg 08h Status2Reg 09h FIFODataReg 0Ah ...
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NXP Semiconductors Table 20. MFRC522 register overview Address Register name (hex) 21h CRCResultReg 22h 23h Reserved 24h ModWidthReg 25h Reserved 26h RFCfgReg 27h GsNReg 28h CWGsPReg 29h ModGsPReg 2Ah TModeReg 2Bh TPrescalerReg 2Ch TReloadReg 2Dh 2Eh TCounterValReg 2Fh Page 3: ...
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NXP Semiconductors 9.3 Register descriptions 9.3.1 Page 0: Command and status 9.3.1.1 Reserved register 00h Functionality is reserved for future use. Table 21. Bit Symbol Access Table 22. Bit 9.3.1.2 CommandReg register Starts and stops command execution. ...
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NXP Semiconductors Table 26. Bit Symbol 7 IRqInv 6 TxIEn 5 RxIEn 4 IdleIEn 3 HiAlertIEn - 2 LoAlertIEn - 1 ErrIEn 0 TimerIEn 9.3.1.4 DivIEnReg register Control bits to enable and disable the passing of interrupt requests. Table 27. ...
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NXP Semiconductors Table 30. All bits in the ComIrqReg register are cleared by software. Bit Symbol 7 Set1 6 TxIRq 5 RxIRq 4 IdleIRq 3 HiAlertIRq 2 LoAlertIRq 1 1 ErrIRq 0 TimerIRq 9.3.1.6 DivIrqReg register Interrupt request bits. Table ...
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NXP Semiconductors 9.3.1.7 ErrorReg register Error bit register showing the error status of the last command executed. Table 33. Bit Symbol Access Table 34: Bit Symbol 7 WrErr 6 TempErr 5 reserved 4 BufferOvfl 3 CollErr 2 CRCErr 1 ParityErr ...
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NXP Semiconductors 9.3.1.8 Status1Reg register Contains status bits of the CRC, interrupt and FIFO buffer. Table 35. Bit Symbol Access Table 36. Bit Symbol 7 reserved 6 CRCOk 5 CRCReady 1 4 IRq 3 TRunning 2 reserved 1 HiAlert 0 ...
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NXP Semiconductors 9.3.1.9 Status2Reg register Contains status bits of the receiver, transmitter and data mode detector. Table 37. Bit Symbol Access Table 38. Bit MFRC522_33 Product data sheet PUBLIC Status2Reg register ...
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NXP Semiconductors 9.3.1.10 FIFODataReg register Input and output of 64 byte FIFO buffer. Table 39. Bit Symbol Access Table 40. Bit 9.3.1.11 FIFOLevelReg register Indicates the number of bytes stored in the FIFO. Table 41. Bit Symbol ...
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NXP Semiconductors Table 44. Bit 9.3.1.13 ControlReg register Miscellaneous control bits. Table 45. Bit Symbol Access Table 46. Bit reserved RxLastBits[2:0] MFRC522_33 Product data sheet PUBLIC ...
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NXP Semiconductors 9.3.1.14 BitFramingReg register Adjustments for bit-oriented frames. Table 47. Bit Symbol Access Table 48. Bit 9.3.1.15 CollReg register Defines the first bit-collision detected on the RF interface. Table 49. Bit ...
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NXP Semiconductors Table 50. Bit Symbol CollPos[4:0] 9.3.1.16 Reserved register 0Fh Functionality is reserved for future use. Table 51. Bit Symbol Access Table 52. Bit 9.3.2 Page 1: Communication 9.3.2.1 Reserved register 10h Functionality ...
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NXP Semiconductors 9.3.2.2 ModeReg register Defines general mode settings for transmitting and receiving. Table 55. Bit Symbol Access Table 56. Bit 9.3.2.3 TxModeReg register Defines the data rate during transmission. Table ...
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NXP Semiconductors Table 58. Bit 9.3.2.4 RxModeReg register Defines the data rate during reception. Table 59. Bit Symbol Access Table 60. Bit MFRC522_33 Product data sheet PUBLIC ...
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NXP Semiconductors Table 60. Bit 9.3.2.5 TxControlReg register Controls the logical behavior of the antenna driver pins TX1 and TX2. Table 61. Bit Symbol InvTx2RF Access Table 62. Bit Symbol 7 InvTx2RFOn 1 6 InvTx1RFOn 1 ...
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NXP Semiconductors 9.3.2.6 TxASKReg register Controls transmit modulation settings. Table 63. Bit Symbol Access Table 64. Bit Symbol 7 reserved 6 Force100ASK reserved 9.3.2.7 TxSelReg register Selects the internal sources for the analog module. Table 65. ...
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NXP Semiconductors Table 66. Bit 9.3.2.8 RxSelReg register Selects internal receiver settings. Table 67. Bit Symbol Access Table 68. Bit MFRC522_33 Product data sheet PUBLIC TxSelReg register bit descriptions Symbol Value ...
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NXP Semiconductors 9.3.2.9 RxThresholdReg register Selects thresholds for the bit decoder. Table 69. Bit Symbol Access Table 70. Bit 9.3.2.10 DemodReg register Defines demodulator settings. Table 71. Bit Symbol Access Table 72. Bit ...
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NXP Semiconductors Table 73. Bit Symbol Access Table 74. Bit 9.3.2.12 Reserved register 1Bh Functionality is reserved for future use. Table 75. Bit Symbol Access Table 76. Bit 9.3.2.13 MfTxReg register Controls some MIFARE ...
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NXP Semiconductors 9.3.2.14 MfRxReg register Table 79. Bit Symbol Access Table 80. Bit Symbol reserved 4 ParityDisable reserved 9.3.2.15 Reserved register 1Eh Functionality is reserved for future use. Table 81. Bit Symbol Access ...
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NXP Semiconductors 9.3.3 Page 2: Configuration 9.3.3.1 Reserved register 20h Functionality is reserved for future use. Table 85. Bit Symbol Access Table 86. Bit 9.3.3.2 CRCResultReg registers Shows the MSB and LSB values of the CRC calculation. ...
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NXP Semiconductors 9.3.3.3 Reserved register 23h Functionality is reserved for future use. Table 91. Bit Symbol Access Table 92. Bit 9.3.3.4 ModWidthReg register Sets the modulation width. Table 93. Bit Symbol Access Table 94. Bit 7 to ...
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NXP Semiconductors 9.3.3.6 RFCfgReg register Configures the receiver gain. Table 97. Bit Symbol Access Table 98. Bit 9.3.3.7 GsNReg register Defines the conductance of the antenna driver pins TX1 and TX2 for the ...
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NXP Semiconductors 9.3.3.8 CWGsPReg register Defines the conductance of the p-driver output during periods of no modulation. Table 101. CWGsPReg register (address 28h); reset value: 20h bit allocation Bit Symbol Access Table 102. CWGsPReg register bit descriptions Bit 7 to ...
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NXP Semiconductors Table 106. TModeReg register bit descriptions Bit Table 107. TPrescalerReg register (address 2Bh); reset value: 00h bit allocation Bit Symbol Access Table 108. TPrescalerReg register bit descriptions Bit 7 to ...
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NXP Semiconductors Remark: The reload value bits are contained in two 8-bit registers. Table 109. TReloadReg (higher bits) register (address 2Ch); reset value: 00h bit allocation Bit Symbol Access Table 110. TReloadReg register higher bit descriptions Bit ...
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NXP Semiconductors Table 116. TCounterValReg register lower bit descriptions Bit 9.3.4 Page 3: Test 9.3.4.1 Reserved register 30h Functionality is reserved for future use. Table 117. Reserved register (address 30h); reset value: 00h bit allocation Bit Symbol ...
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NXP Semiconductors Table 122. TestSel2Reg register bit descriptions Bit Symbol 7 TstBusFlip 1 6 PRBS9 5 PRBS15 TestBusSel [4:0] 9.3.4.4 TestPinEnReg register Enables the test bus pin output driver. Table 123. TestPinEnReg register (address 33h); reset value: ...
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NXP Semiconductors Table 126. TestPinValueReg register bit descriptions Bit TestPinValue 0 9.3.4.6 TestBusReg register Shows the status of the internal test bus. Table 127. TestBusReg register (address 35h); reset value: xxh bit allocation Bit Symbol Access ...
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NXP Semiconductors Table 130. AutoTestReg register bit descriptions Bit 9.3.4.8 VersionReg register Shows the MFRC522 software version. Table 131. VersionReg register (address 37h); reset value: xxh bit allocation Bit Symbol Access Table ...
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NXP Semiconductors Table 134. AnalogTestReg register bit descriptions Bit AnalogSelAux1 AnalogSelAux2 [1] Remark: Current source output; the use pull-down resistor on AUXn is recommended. MFRC522_33 Product data sheet PUBLIC Symbol Value ...
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NXP Semiconductors 9.3.4.10 TestDAC1Reg register Defines the test value for TestDAC1. Table 135. TestDAC1Reg register (address 39h); reset value: xxh bit allocation Bit Symbol Access Table 136. TestDAC1Reg register bit descriptions Bit 9.3.4.11 TestDAC2Reg register ...
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NXP Semiconductors Table 141. Reserved register (address 3Ch); reset value: FFh bit allocation Bit Symbol Access Table 142. Reserved register bit descriptions Bit Table 143. Reserved register (address 3Dh); reset value: 00h bit allocation Bit Symbol Access ...
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NXP Semiconductors 10. MFRC522 command set 10.1 General description The MFRC522 operation is determined by a state machine capable of performing a set of commands. A command is executed by writing a command code (see CommandReg register. Arguments and/or data ...
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NXP Semiconductors 10.3.1 MFRC522 command descriptions 10.3.1.1 Idle Places the MFRC522 in Idle mode. The Idle command also terminates itself. 10.3.1.2 Mem Transfers 25 bytes from the FIFO buffer to the internal buffer. To read out the 25 bytes from ...
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NXP Semiconductors 10.3.1.7 Receive The MFRC522 activates the receiver path and waits for a data stream to be received. The correct settings must be chosen before starting this command. This command automatically terminates when the data stream ends. This is ...
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NXP Semiconductors This command automatically terminates when the MIFARE card is authenticated and the Status2Reg register’s MFCrypto1On bit is set to logic 1. This command does not terminate automatically if the card does not answer, so the timer must be ...
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NXP Semiconductors 11. Limiting values Table 150. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V analog supply voltage DDA V digital supply voltage DDD V PVDD supply voltage DD(PVDD) V TVDD supply voltage ...
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NXP Semiconductors 14. Characteristics Table 153. Characteristics Symbol Parameter Input characteristics Pins EA, I2C and NRSTPD I input leakage current LI V HIGH-level input voltage IH V LOW-level input voltage IL Pin MFIN I input leakage current LI V HIGH-level ...
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NXP Semiconductors Table 153. Characteristics …continued Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I HIGH-level output current OH I LOW-level output current OL Output characteristics Pin MFOUT V HIGH-level output voltage OH V LOW-level output ...
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NXP Semiconductors Table 153. Characteristics …continued Symbol Parameter V LOW-level output voltage OL Current consumption I power-down current pd I digital supply current DDD I analog supply current DDA I PVDD supply current DD(PVDD) I TVDD supply current DD(TVDD) I ...
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NXP Semiconductors [3] I depends on the overall load at the digital pins. DD(PVDD) [4] I depends on V and the external circuit connected to pins TX1 and TX2. DD(TVDD) DD(TVDD) [5] During typical circuit operation, the overall current is ...
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NXP Semiconductors Table 155. I Symbol Parameter f SCL t HD;STA t SU;STA t SU;STO t LOW t HIGH t HD;DAT t SU;DAT BUF SCK MOSI MISO NSS Fig 25. Timing ...
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NXP Semiconductors SDA SCL Fig 26. Timing for Fast and Standard mode devices on the I MFRC522_33 Product data sheet PUBLIC SU;DAT t t LOW HIGH t HD;STA t HD;DAT S Rev. 3 ...
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NXP Semiconductors 15. Application information A typical application diagram using a complementary antenna connection to the MFRC522 is shown in The antenna tuning and RF part matching is described in the application note Ref. 2. MICRO- PROCESSOR Fig 27. Typical ...
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NXP Semiconductors 16. Test information 16.1 Test signals 16.1.1 Self test The MFRC522 has the capability to perform a digital self test. The self test is started by using the following procedure: 1. Perform a soft reset. 2. Clear the ...
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NXP Semiconductors Table 156. Test bus signals: TestBusSel[4:0] = 07h Pins Table 157. Test bus signals: TestBusSel[4:0] = 0Dh Pins 16.1.3 Test signals on pins AUX1 or ...
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NXP Semiconductors Table 158. Test signal descriptions AnalogSelAux1[3:0] or AnalogSelAux2[3:0] value 1101 1110 1111 16.1.3.1 Example: Output test signals TestDAC1 and TestDAC2 The AnalogTestReg register is set to 11h. The output on pin AUX1 has the test signal TestDAC1 and ...
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NXP Semiconductors (1) MinLevel (1 V/div) on pin AUX2. (2) Corr1 (1 V/div) on pin AUX1. (3) RF field. Fig 29. Output test signals Corr1 on pin AUX1 and MinLevel on pin AUX2 16.1.3.3 Example: Output test signals ADC channel ...
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NXP Semiconductors 16.1.3.4 Example: Output test signals RxActive and TxActive Figure 31 The AnalogTestReg register is set to CDh. • At 106 kBd, RxActive is HIGH during data bits, parity and CRC reception. Start bits are not included • At ...
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NXP Semiconductors 16.1.3.5 Example: Output test signal RX data stream Figure 32 register’s TestBusSel[4:0] bits are set to 07h to enable test bus signals on pins D1 to D6; see Section 16.1.2 on page 06h (pin D6 = s_data) and ...
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NXP Semiconductors 17. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area ...
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NXP Semiconductors Detailed package information can be found at: http://www.nxp.com/package/SOT617-1.html. 18. Handling information Moisture Sensitivity Level (MSL) evaluation has been performed according to SNW-FQ-225B rev.04/07/07 (JEDEC J-STD-020C) . MSL for this package is level 1 which means 260 C convection ...
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NXP Semiconductors 20. Abbreviations Table 159. Abbreviations Acronym ADC BPSK CRC CW DAC HBM LSB MISO MM MOSI MSB NRZ NSS PLL PRBS RX SOF SPI TX UART 21. References [1] Application note — MFRC52x Reader IC ...
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NXP Semiconductors 22. Revision history Table 160. Revision history Document ID Release date MFRC522_33 20091026 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have ...
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NXP Semiconductors 23. Legal information 23.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors 24. Contact information For more information, please visit: For sales office addresses, please send an email to: MFRC522_33 Product data sheet PUBLIC http://www.nxp.com salesaddresses@nxp.com Rev. 3 — 26 October 2009 112133 MFRC522 Contactless reader IC © NXP B.V. ...
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NXP Semiconductors 25. Tables Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2 Table 2. Ordering information . . . . . . ...
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NXP Semiconductors Table 69. RxThresholdReg register (address 18h); reset value: 84h bit allocation . . . . . . . . . . . . . . . . . .51 Table 70. RxThresholdReg register bit descriptions . . . ...
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NXP Semiconductors Table 135.TestDAC1Reg register (address 39h); reset value: xxh bit allocation . . . . . . . . . . . . . .65 Table 136.TestDAC1Reg register bit descriptions . . . . . .65 Table 137.TestDAC2Reg register ...
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NXP Semiconductors 26. Figures Fig 1. Simplified block diagram of the MFRC522 Fig 2. Detailed block diagram of the MFRC522 . . . . . . . .4 Fig 3. Pinning configuration HVQFN32 (SOT617-1) ...
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NXP Semiconductors 27. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 General description . . ...
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NXP Semiconductors 9.3.4.6 TestBusReg register . . . . . . . . . . . . . . . . . . . . 62 9.3.4.7 AutoTestReg register . . . . . . . . . . . ...