UJA1069TW PHILIPS [NXP Semiconductors], UJA1069TW Datasheet - Page 39

• Manufacturer Part Number: UJA1069TW
• Description: LIN fail-safe system basis chip
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
UJA1069_2
Preliminary data sheet
6.13.2 Forced normal mode
For system evaluation purposes the UJA1069 offers the Forced normal mode. This mode
is strictly for evaluation purposes only. In this mode the characteristics as defined in
Section 9
In Forced normal mode the SBC behaves as follows:
Forced normal mode is activated by applying the correct V
TEST pin during first battery connection.
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SPI access (writing and reading) is blocked
Watchdog disabled
Interrupt monitoring disabled
Reset monitoring disabled
Reset lengthening disabled
All transitions to Fail-safe mode are disabled, except a V1 undervoltage for more than
t
V1 is started with the long reset time t
performed until V1 is restored (normal behavior), and the SBC stays in Forced normal
mode; in case of an overload at V1 > t
V3 is on; overload protection active
LIN is in Active mode and cannot switch to Off-line mode
INH/LIMP pin is HIGH
SYSINH is HIGH
EN pin at same level as RSTN pin
V1(CLT)
and
Section 10
Rev. 02 — 5 March 2007
cannot be guaranteed.
RSTNL
V1(CLT)
. In case of a V1 undervoltage, a reset is
Fail-safe mode is entered
LIN fail-safe system basis chip
th(TEST)
input voltage at the
UJA1069
© NXP B.V. 2007. All rights reserved.
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