UJA1078 NXP [NXP Semiconductors], UJA1078 Datasheet - Page 43

• Manufacturer Part Number: UJA1078
• Description: High-speed CAN/dual LIN core system basis chip
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
[5]
[6]
[7]
UJA1078_2
Product data sheet
A system reset will be performed if the watchdog is in Window mode and is triggered less than t
period (or in the first half of the watchdog period).
The nominal watchdog period is programmed via the NWP control bits in the WD_and_Status register (see
Window mode only.
The watchdog will be reset if it is in window mode and is triggered at least t
watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than
t
trig(wd)2
after the start of the watchdog period (watchdog overflows).
Fig 15. Timing test circuit for CAN transceiver
Fig 16. CAN transceiver timing diagram
TXDC
CANH
CANL
V
RXDC
t
t
d(TXDCL-RXDCL)
O(dif)bus
d(TXDC-busdom)
C RXDC
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 27 May 2010
RXDC
TXDC
SBC
GND
BAT
t
d(busdom-RXDC)
High-speed CAN/dual LIN core system basis chip
t
d(TXDCH-RXDCH)
CANH
CANL
t
trig(wd)1
d(TXDC-busrec)
, but not more than t
R CANH − R CANL
trig(wd)1
015aaa079
trig(wd)2
after the start of the watchdog
C CANH − C CANL
0.9 V
0.5 V
Table
, after the start of the
UJA1078
© NXP B.V. 2010. All rights reserved.
t
d(busrec-RXDC)
4); valid in watchdog
HIGH
LOW
dominant
recessive
HIGH
LOW
015aaa151
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