MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 332

• Manufacturer Part Number: MC68HC908AP16CFA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Multi-Master IIC Interface (MMIIC)
16.6.4 MMIIC Status Register (MMSR)
Data Sheet
332
Address:
MMRXIF — MMIIC Receive Interrupt Flag
MMTXIF — MMIIC Transmit Interrupt Flag
MMATCH — MMIIC Address Match Flag
Reset:
Read: MMRXIF
Write:
Freescale Semiconductor, Inc.
This flag is set after the data receive register (MMDRR) is loaded with
a new received data. Once the MMDRR is loaded with received data,
no more received data can be loaded to the MMDRR register until the
CPU reads the data from the MMDRR to clear MMRXBF flag.
MMRXIF generates an interrupt request to CPU if the MMIEN bit in
MMCR is also set. This bit is cleared by writing "0" to it or by reset; or
when the MMEN = 0.
This flag is set when data in the data transmit register (MMDTR) is
downloaded to the output circuit, and that new data can be written to
the MMDTR. MMTXIF generates an interrupt request to CPU if the
MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it
or when the MMEN = 0.
This flag is set when the received data in the data receive register
(MMDRR) is a calling address which matches with the address or its
extended addresses (MMEXTAD = 1) specified in the address
register (MMADR). The MMATCH flag is set at the 9th clock of the
calling address and will be cleared on the 9th clock of the next
receiving data. Note: slave transmits do not clear MMATCH.
For More Information On This Product,
1 = New data in data receive register (MMDRR)
0 = No data received
1 = Data transfer completed
0 = Data transfer in progress
$004B
Bit 7
0
0
Figure 16-7. MMIIC Status Register (MMSR)
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= Unimplemented
MMTXIF MMATCH MMSRW MMRXAK
6
0
0
5
0
4
0
MC68HC908AP Family — Rev. 2.5
3
1
MMCRCBF
2
0
MMTXBE MMRXBF
1
1
MOTOROLA
Bit 0
0