MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 396

• Manufacturer Part Number: MC68HC908AP16CFA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Computer Operating Properly (COP)
21.3 I/O Signals
21.3.1 ICLK
21.3.2 STOP Instruction
Data Sheet
396
NOTE:
NOTE:
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler counter. If not cleared by software, the COP counter overflows
and generates an asynchronous reset after 2
cycles, depending on the state of the COP rate select bit, COPRS, in the
CONFIG1 register. With a 2
ICLK gives a COP timeout period of 341ms. Writing any value to location
$FFFF before an overflow occurs prevents a COP reset by clearing the
COP counter and stages 12 through 5 of the prescaler.
Service the COP immediately after reset and before entering or after
exiting STOP Mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 ICLK cycles and sets the COP
bit in the SIM reset status register (SRSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ1 is held
at V
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
The following paragraphs describe the signals shown in
ICLK is the internal oscillator output signal. See
Specifications
The STOP instruction clears the COP prescaler.
Freescale Semiconductor, Inc.
TST
For More Information On This Product,
. During the break state, V
Go to: www.freescale.com
for ICLK frequency specification.
13
– 2
4
TST
ICLK cycle overflow option, a 24-kHz
on the RST pin disables the COP.
MC68HC908AP Family — Rev. 2.5
18
– 2
Section 24. Electrical
4
or 2
13
Figure
– 2
MOTOROLA
4
ICLK
21-1.