74VCXH16374DT ONSEMI [ON Semiconductor], 74VCXH16374DT Datasheet

74VCXH16374DT

Manufacturer Part Number

74VCXH16374DT

Description

Low−Voltage 1.8/2.5/3.3V 16-Bit D−Type Flip−Flop With 3.6 V-Tolerant Inputs and Outputs (3-State, Non-Inverting)

Manufacturer

ONSEMI [ON Semiconductor]

Datasheet

1.74VCXH16374DT.pdf (11 pages)

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74VCXH16374

Low−Voltage 1.8/2.5/3.3V

16−Bit D−Type Flip−Flop

With 3.6 V−Tolerant Inputs and Outputs

(3−State, Non−Inverting)

16−bit D−type flip−flop. It is designed for very high−speed, very

low−power operation in 1.8 V, 2.5 V or 3.3 V systems. The VCXH16374

is byte controlled, with each byte functioning identically, but

independently. Each byte has separate Output Enable and Clock Pulse

inputs. These control pins can be tied together for full 16−bit operation.

voltages it may encounter on either inputs or outputs when interfacing

to 3.3 V busses. It is guaranteed to be overvoltage tolerant to 3.6V.

individual D−type inputs and 3.6 V−tolerant 3−state outputs. The

clocks (CPn) and Output Enables (OEn) are common to all flip−flops

within the respective byte. The flip−flops will store the state of

individual D inputs that meet the setup and hold time requirements on

the LOW−to−HIGH Clock (CP) transition. With the OE LOW, the

contents of the flip−flops are available at the outputs. When the OE is

HIGH, the outputs go to the high impedance state. The OE input level

does not affect the operation of the flip−flops. The data inputs include

active bushold circuitry, eliminating the need for external pullup

resistors to hold unused or floating inputs at a valid logic state.

Features

•

*To ensure the outputs activate in the 3−state condition, the output enable pins

**For additional information on our Pb−Free strategy and soldering details,

June, 2006 − Rev. 5

should be connected to V

is determined by the current sinking capability of the output connected to the

OE pin.

please download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

The 74VCXH16374 is an advanced performance, non−inverting

When operating at 2.5 V (or 1.8 V) the part is designed to tolerate

The 74VCXH16374 consists of 16 edge−triggered flip−flops with

Logic State

Substantially Reduces System Power Requirements

Designed for Low Voltage Operation: V

3.6 V Tolerant Inputs and Outputs

High Speed Operation: 3.0 ns max for 3.0 V to 3.6V

Static Drive: ±24 mA Drive at 3.0 V

Supports Live Insertion and Withdrawal

Includes Active Bushold to Hold Unused or Floating Inputs at a Valid

Near Zero Static Supply Current in All Three Logic States (20 mA)

Latchup Performance Exceeds ±250 mA @ 125°C

ESD Performance: Human Body Model >2000 V

All Devices in Package TSSOP are Inherently Pb−Free**

OFF

Specification Guarantees High Impedance When V

±18 mA Drive at 2.3 V

±6 mA Drive at 1.65 V

Machine Model >200 V

through a pullup resistor. The value of the resistor

3.9 ns max for 2.3 V to 2.7V

7.8 ns max for 1.65 V to 1.95V

= 1.65 V − 3.6 V

= 0 V*

PIN NAMES

†For information on tape and reel specifications,

74VCXH16374DT

74VCXH16374DTR

Pins

OEn

CPn

D0−D15

O0−O15

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

DT SUFFIX

CASE 1201

TSSOP−48

Device

ORDERING INFORMATION

http://onsemi.com

Function

Output Enable Inputs

Clock Pulse Inputs

Inputs

Outputs

= Assembly Location

= Wafer Lot

= Year

= Work Week

(Pb−Free)

Package

TSSOP

MARKING DIAGRAM

Publication Order Number:

VCXH16374

AWLYYWW

74VCXH16374/D

2500 / Reel

Shipping

39 / Rail

†

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74VCXH16374DT Summary of contents

Page 1

... June, 2006 − Rev PIN NAMES Pins OEn = 1.65 V − 3.6 V CPn CC D0−D15 O0−O15 74VCXH16374DT 74VCXH16374DTR = †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1 http://onsemi.com MARKING DIAGRAM 48 ...

Page 2

OE1 CP1 GND GND ...

Page 3

TRUTH TABLE Inputs CP1 OE1 D0 ↑ ↑ High Voltage Level L = Low Voltage Level Z = High Impedance State ↑ = Low−to−High Transition X = High ...

Page 4

DC ELECTRICAL CHARACTERISTICS Symbol Characteristic V HIGH Level Input Voltage (Note LOW Level Input Voltage (Note HIGH Level Output Voltage OH V LOW Level Output Voltage OL I Input Leakage Current I I Minimum ...

Page 5

AC CHARACTERISTICS (Note Symbol Parameter f Clock Pulse Frequency max t Propagation Delay PLH t CP−to−On PHL t Output Enable Time to PZH t High and Low Level PZL t Output Disable Time From PHZ ...

Page 6

DYNAMIC SWITCHING CHARACTERISTICS Symbol Characteristic V Dynamic LOW Peak Voltage OLP (Note 9) V Dynamic LOW Valley Voltage OLV (Note 9) V Dynamic HIGH Valley Voltage OHV (Note 10) 9. Number of outputs defined as “n”. Measured with “n−1” outputs ...

Page 7

CPn Vm f max PLH PHL On Vm WAVEFORM 1 − PROPAGATION DELAYS, SETUP AND HOLD TIMES 2.0 ns, 10 MHz; t ...

Page 8

PULSE GENERATOR R T Figure 6. Test Circuit Table 2. TEST CIRCUIT TEST PLH PHL PZL PLZ PZH PHZ equivalent (Includes jig and probe capacitance) L ...

Page 9

CPn Vm f max PLH PHL On Vm WAVEFORM 4 − PROPAGATION DELAYS, SETUP AND HOLD TIMES 2.0 ns, 10 MHz; t ...

Page 10

PULSE GENERATOR R T Figure 9. Test Circuit Table 4. TEST CIRCUIT TEST PLH PHL PZL PLZ PZH PHZ equivalent (Includes jig and probe capacitance) L ...

Page 11

K 48X REF 0.12 (0.005 PIN 1 IDENT. −V− 0.076 (0.003) −T− SEATING PLANE ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further ...

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