ATA6602-PLQW ATMEL [ATMEL Corporation], ATA6602-PLQW Datasheet - Page 188

• Manufacturer Part Number: ATA6602-PLQW
• Description: Microcontroller with LIN Transceiver, 5V Regulator and Watchdog
• Manufacturer: ATMEL [ATMEL Corporation]

4.16.1.4
4.16.1.5
188
ATA6602/ATA6603
SPI Status Register – SPSR
SPI Data Register – SPDR
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-
ter causes the Shift Register Receive buffer to be read.
• Bit 7 – SPIF: SPI Interrupt Flag
• Bit 6 – WCOL: Write COLlision Flag
• Bit 5..1 – Res: Reserved Bits
• Bit 0 – SPI2X: Double SPI Speed Bit
Initial Value
Read/Write
Initial Value
Read/Write
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the
SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared
by first reading the SPI Status Register with SPIF set, then accessing the SPI Data Register
(SPDR).
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL
set, and then accessing the SPI Data Register.
These bits are reserved bits in the ATA6602/ATA6603 and will always read as zero.
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the
SPI is in Master mode (see
period will be two CPU clock periods. When the SPI is configured as Slave, the SPI is only
guaranteed to work at fosc/4 or lower.
The SPI interface on the ATA6602/ATA6603 is also used for program memory and
EEPROM downloading or uploading. See
gramming and verification.
Bit
Bit
MSB
SPIF
R/W
X
R
7
7
0
WCOL
R/W
X
R
6
6
0
Table 4-69 on page
R/W
X
5
R
5
–
0
R/W
X
4
R
4
–
0
“Serial Downloading” on page 312
R/W
X
3
R
3
–
0
187). This means that the minimum SCK
R/W
X
2
R
2
–
0
R/W
X
1
R
1
–
0
SPI2X
LSB
R/W
R/W
X
0
0
0
4921C–AUTO–01/07
for serial pro-
Undefined
SPDR
SPSR