ATA6602-PLQW ATMEL [ATMEL Corporation], ATA6602-PLQW Datasheet - Page 41

• Manufacturer Part Number: ATA6602-PLQW
• Description: Microcontroller with LIN Transceiver, 5V Regulator and Watchdog
• Manufacturer: ATMEL [ATMEL Corporation]

4.5.2.1
4.5.3
4.5.3.1
4921C–AUTO–01/07
EEPROM Data Memory
Data Memory Access Times
EEPROM Read/Write Access
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 4-10. On-chip Data SRAM Access Cycles
The ATA6602/ATA6603 contains 512 bytes of data EEPROM memory. It is organized as a sep-
arate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
The section
Programming in SPI or Parallel Programming mode.
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
however, lets the user software detect when the next byte can be written. If the user code con-
tains instructions that write the EEPROM, some precautions must be taken. In heavily filtered
power supplies, V
some period of time to run at a voltage lower than specified as minimum for the clock frequency
used. See
these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
“Preventing EEPROM Corruption” on page 46
Address
“Memory Programming” on page 297
clk
Data
Data
WR
RD
CPU
CC
is likely to rise or fall slowly on power-up/down. This causes the device for
Compute Address
T1
Memory Access Instruction
Address valid
CPU
contains a detailed description on EEPROM
Table 4-3 on page
T2
cycles as described in
for details on how to avoid problems in
ATA6602/ATA6603
Next Instruction
T3
44. A self-timing function,
Figure
4-10.
41