ATA6602-PLQW ATMEL [ATMEL Corporation], ATA6602-PLQW Datasheet - Page 35

• Manufacturer Part Number: ATA6602-PLQW
• Description: Microcontroller with LIN Transceiver, 5V Regulator and Watchdog
• Manufacturer: ATMEL [ATMEL Corporation]

4.4.7
4921C–AUTO–01/07
Instruction Execution Timing
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 4-5
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 4-5.
Figure 4-6 on page 36
cycle an ALU operation using two register operands is executed, and the result is stored back to
the destination register.
Initial Value
Read/Write
Bit
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
shows the parallel instruction fetches and instruction executions enabled by the Har-
RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
SP15
SP7
R/W
R/W
The Parallel Instruction Fetches and Instruction Executions
15
7
clk
shows the internal timing concept for the Register File. In a single clock
SP14
R/W
R/W
SP6
CPU
14
6
SP13
SP5
R/W
R/W
13
5
CPU
T1
, directly generated from the selected clock source for the
SP12
SP4
R/W
R/W
12
4
SP11
SP3
R/W
R/W
T2
11
3
ATA6602/ATA6603
SP10
R/W
SP2
R/W
10
2
T3
R/W
R/W
SP9
SP1
9
1
SP8
SP0
R/W
R/W
T4
8
0
SPH
SPL
35