HD151BF854SSEL RENESAS [Renesas Technology Corp], HD151BF854SSEL Datasheet - Page 10

• Manufacturer Part Number: HD151BF854SSEL
• Description: 2.5 V PLL Clock Buffer for DDR Application
• Manufacturer: RENESAS [Renesas Technology Corp]

HD151BF854
Switching Characteristics
Ta = 25 C, VDD = AVDD = 2.5V
Item
Period jitter
Half period jitter
Cycle to cycle jitter
Static phase offset
Output clock skew
Operating clock frequency f
Application clock
frequency
Slew rate
Stabilization time
Notes: Target of design, not 100% tested in production.
Rev.4, Jan. 2003, page 8 of 11
1. The PLL must be able to handle spread spectrum induced skew. (the specification for this
2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in
3. Application clock frequency indicates a range over which the PLL must meet all timing
4. Assumes equal wire length and loading on the clock output and feedback path.
5. Static phase offset does not include jitter.
6. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of it’s
7. Period jitter defines the largest variation in clock period, around a nominal clock period.
8. Period jitter and half period jitter are separate specifications that must be met independently of
frequency modulation can be found in the latest Intel PC100 Registered DIMM specification)
which it is not required to meet the other timing parameters. (Used for low speed system debug.)
parameters.
feedback signal to it’s reference signal after power on.
each other.
Symbol
t
t
t
t
t
f
PER
HPER
CC
sPE
sk
CLK(O)
CLK(A)
Min
—
—
—
—
—
60
80
1.0
—
Typ
|75|
|120|
|75|
|150|
150
—
166
—
—
Max
—
—
—
—
—
210
210
2.0
0.1
Unit Test Conditions & Notes
ps
ps
ps
ps
ps
MHz *
MHz *
V/ns 20% to 80%
ms
*
*
*
*
7, 8
8
4, 5
1, 2
1, 3
6