HD151BF854SSEL RENESAS [Renesas Technology Corp], HD151BF854SSEL Datasheet - Page 9
HD151BF854SSEL
Manufacturer Part Number
HD151BF854SSEL
Description
2.5 V PLL Clock Buffer for DDR Application
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD151BF854SSEL.pdf
(13 pages)
Electrical Characteristics
Item
Input clamp voltage
(All inputs)
Output voltage
Input current
Analog supply current
Dynamic supply current
Input capacitance*
Delta input capacitance*
Notes: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended
2. Target of design, not 100% tested in production.
operating conditions.
2
2
Symbol Min
V
V
V
I
AI
DI
C
C
I
IK
OH
OL
I
Di
CC
CC
—
VDD–0.2
1.7
—
—
–10
—
—
2.5
–0.25
Typ *
—
—
—
—
—
—
—
250
—
—
1
VDD
Max
–1.2
—
0.2
0.6
10
12
300
3.5
0.25
Unit
V
V
µA
mA
mA
pF
pF
Test Conditions
I
I
V
I
I
I
V
VDD = 2.7 V, CLKIN, FBIN
VDD = AVDD = 2.7 V,
170 MHz
170 MHz
All Yn, Yn, = open
CLKIN and FBIN
VDD = AVDD = 2.7 V,
I
OH
OH
OL
OL
I
= –18 mA, VDD = 2.3 V
= 0 V or 2.7 V,
= 100 µA, VDD = 2.3 to 2.7 V
= 12 mA, VDD = 2.3 V
= –100 µA, VDD = 2.3 to 2.7
= –12 mA, VDD = 2.3 V
Rev.4, Jan. 2003, page 7 of 11
HD151BF854