HD151BF854SSEL RENESAS [Renesas Technology Corp], HD151BF854SSEL Datasheet - Page 6

• Manufacturer Part Number: HD151BF854SSEL
• Description: 2.5 V PLL Clock Buffer for DDR Application
• Manufacturer: RENESAS [Renesas Technology Corp]

HD151BF854
Pin Functions
Pin name
AGND
AVDD
CLKIN
FBIN
FBOUT
GND
VDD
Y
Y
NC
Rev.4, Jan. 2003, page 4 of 11
No.
11
10
8
20
19
6, 15, 28
3, 12, 23
2, 4, 13,
17, 24, 26
1, 5, 14,
16, 25, 27
7, 9, 18, 21,
22
Type
Ground
Power
Input
Input
Output
Ground
Power
Output
Output
NC
Description
Analog ground. AGND provides the ground reference for the
analog circuitry.
Analog power supply. AVDD provides the power reference for
the analog circuitry. In addition, AVDD can be used to bypass
the PLL for test purposes. When AVDD is strapped to ground,
PLL is bypassed and CLK is buffered directly to the device
outputs.
Clock input. CLKIN provides the clock signal to be distributed by
the HD151BF854 clock buffer. CLK is used to provide the
reference signal to the integrated PLL that generates the clock
output signals. CLK must have a fixed frequency and fixed
phase for the PLL to obtain phase lock. Once the circuit is
powered up and a valid CLK signal is applied, a stabilization time
is required for the PLL to phase lock the feedback signal to its
reference signal.
Feedback input. FBIN provides the feedback signal to the
internal PLL. FBIN must be hard-wired to FBOUT to complete
the PLL. The integrated PLL synchronizes CLKIN and FBIN so
that there is nominally zero phase error between CLKIN and
FBIN.
Feedback output. FBOUT is dedicated for external feedback. It
switches at the same frequency as CLK. When externally wired
to FBIN, FBOUT completes the feedback loop of the PLL.
Ground
Power supply
Clock outputs. (+Clock) These outputs provide low-skew copies
of CLK.
Bar clock outputs. (–Clock) These outputs provide low-skew
copies of CLK.
Don’t connect any VDD or GND.