IS42S16100-10TI ISSI [Integrated Silicon Solution, Inc], IS42S16100-10TI Datasheet

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IS42S16100-10TI

Manufacturer Part Number
IS42S16100-10TI
Description
512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
Manufacturer
ISSI [Integrated Silicon Solution, Inc]
Datasheet
PIN DESCRIPTIONS
IS42S16100
FEATURES
• Clock frequency: 166, 143, 100 MHz
• Fully synchronous; all signals referenced to a
• Two banks can be operated simultaneously and
• Dual internal bank controlled by A11 (bank
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
• Programmable burst sequence:
• Auto refresh, self refresh
• 4096 refresh cycles every 128 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
• Burst termination by burst stop and precharge
• Byte controlled by LDQM and UDQM
• Package 400-mil 50-pin TSOP II
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. C
11/01/01
512K Words x 16 Bits x 2 Banks (16-MBIT)
SYNCHRONOUS DYNAMIC RAM
A0-A11
A0-A10
A11
A0-A7
I/O0 to I/O15
CLK
CKE
CS
RAS
positive clock edge
independently
select)
– (1, 2, 4, 8, full page)
Sequential/Interleave
operations capability
command
Address Input
Row Address Input
Bank Select Address
Column Address Input
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
1-800-379-4774
DESCRIPTION
ISSI
organized as a 524,288-word x 16-bit x 2-bank for
improved performance. The synchronous DRAMs
achieve high-speed data transfer using pipeline
architecture. All inputs and outputs signals refer to the
rising edge of the clock input.
PIN CONFIGURATIONS
50-Pin TSOP (Type II)
CAS
WE
LDQM
UDQM
Vcc
GND
VccQ
GNDQ
NC
’s 16Mb Synchronous DRAM IS42S16100 is
GNDQ
GNDQ
VCCQ
VCCQ
LDQM
I/O7
VCC
CAS
RAS
VCC
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
A11
A10
WE
CS
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Column Address Strobe Command
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
NOVEMBER 2001
ISSI
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
GND
I/O15
I/O14
GNDQ
I/O13
I/O12
VCCQ
I/O11
I/O10
GNDQ
I/O9
I/O8
VCCQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
GND
®
1

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