M36W0R5020B0ZAQ STMICROELECTRONICS [STMicroelectronics], M36W0R5020B0ZAQ Datasheet

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M36W0R5020B0ZAQ

Manufacturer Part Number
M36W0R5020B0ZAQ
Description
32 Mbit (2Mb x16, Multiple Bank, Burst) Flash Memory and 4 Mbit SRAM, 1.8V Supply Multi-Chip Package
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
FEATURES SUMMARY
FLASH MEMORY
December 2004
MULTI-CHIP PACKAGE
SUPPLY VOLTAGE
LOW POWER CONSUMPTION
ELECTRONIC SIGNATURE
PACKAGE
PROGRAMMING TIME
MEMORY BLOCKS
SYNCHRONOUS / ASYNCHRONOUS READ
DUAL OPERATIONS
1 die of 32 Mbit (2Mb x 16) Flash Memory
1 die of 4 Mbit (256Kb x16) SRAM
V
Manufacturer Code: 20h
Device Code (Top Flash Configuration):
8814h
Device Code (Bottom Flash
Configuration): 8815h
Compliant with Lead-Free Soldering
Processes
Lead-Free Versions
8µs by Word typical for Fast Factory
Program
Double/Quadruple Word Program option
Enhanced Factory Program options
Multiple Bank Memory Array: 4 Mbit
Banks
Parameter Blocks (Top or Bottom
location)
Synchronous Burst Read mode: 66MHz
Asynchronous/ Synchronous Page Read
mode
Random Access: 70ns
Program Erase in one Bank while Read in
others
No delay between Read and Write
operations
DDF
= V
32 Mbit (2Mb x16, Multiple Bank, Burst) Flash Memory
DDQ
and 4 Mbit SRAM, 1.8V Supply Multi-Chip Package
= V
DDS
= 1.7 to 1.95V
Figure 1. Package
SRAM
BLOCK LOCKING
SECURITY
COMMON FLASH INTERFACE (CFI)
100,000 PROGRAM/ERASE CYCLES per
BLOCK
ACCESS TIME: 70ns
LOW V
POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
All blocks locked at Power-up
Any combination of blocks can be locked
WP
128-bit user programmable OTP cells
64-bit unique device number
DDS
F
for Block Lock-Down
M36W0R5020B0
M36W0R5020T0
DATA RETENTION: 1.0V
Stacked TFBGA88
(ZAQ)
FBGA
1/26

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M36W0R5020B0ZAQ Summary of contents

Page 1

... Mbit (2Mb x16, Multiple Bank, Burst) Flash Memory and 4 Mbit SRAM, 1.8V Supply Multi-Chip Package FEATURES SUMMARY MULTI-CHIP PACKAGE – 1 die of 32 Mbit (2Mb x 16) Flash Memory – 1 die of 4 Mbit (256Kb x16) SRAM SUPPLY VOLTAGE – DDF DDQ DDS LOW POWER CONSUMPTION ELECTRONIC SIGNATURE – ...

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... Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DDF V Supply Voltage DDS V Supply Voltage DDQ V Program Supply Voltage PPF V Ground FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Main Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 FLASH MEMORY COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SRAM COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. SRAM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SRAM OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/ ...

Page 3

... Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7. AC Measurement Load Circuit Table 5. Device Capacitance Table 6. Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 7. Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 8. SRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. SRAM Read Mode AC Waveforms, Address Controlled with UB Figure 9. SRAM Read AC Waveforms, G Figure 10.SRAM Standby AC Waveforms Table 9 ...

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... Note: 1. A20-A18 are address inputs for the Flash memory com- AI08754b (1) Address Inputs Common Data Input/Output Flash Memory Power Supply Common Flash and SRAM Power Supply for I/O Buffers Common Flash Optional Supply Voltage for Fast Program and Erase ...

Page 5

Figure 3. TFBGA Connections (Top view through package A18 A17 DQ8 G S DQ0 ...

Page 6

... M58WR032FT/B datasheet). Flash Reset (RP ). The Reset input provides a F hardware reset of the memory. When Reset the memory is in Reset mode: the outputs are IL high impedance and the current consumption is reduced to the Reset Supply Current I Table 6., Flash Memory DC Characteristics - Cur- 6/26 and Table 1 ...

Page 7

... Byte Enable input enables the lower byte for SRAM (DQ0-DQ7 active low Supply Voltage. V DDF DDF supply to the internal core of the Flash memory component the main power supply for all Flash memory operations (Read, Program and Erase). V Supply Voltage. V DDS DDS supply to the internal core of the SRAM device ...

Page 8

... 8/26 most common example is simultaneous read oper- ations on the Flash memory and SRAM compo- nents which would result in a data bus contention. and Therefore it is recommended to put the other de- S vices in the high impedance state when reading the selected device. ...

Page 9

... IH Disable V Flash Standby Flash Reset SRAM Read Flash Memory must be disabled SRAM Write Output Disable Any Flash mode is allowed. SRAM Standby Note Don't care can be tied the valid address has been previously latched Depends ...

Page 10

... M36W0R5020T0, M36W0R5020B0 FLASH MEMORY COMPONENT The M36W0R5020T0 and M36W0R5020B0 con- tain a 32 Mbit Flash memory. For detailed informa- tion on how to use it, see the M58WR032FT/B SRAM COMPONENT The M36W0R5020T0 and M36W0R5020B0 con- tain a 4 Mbit SRAM. See Figure 5., SRAM Block Diagram in conjunction with the Figure 5 ...

Page 11

SRAM OPERATIONS There are five standard operations that control the device. These are Read, Write, Standby/Power- down, Data Retention and Output Disable. Read. Read operations are used to output the contents of the SRAM Array. The device is in Byte ...

Page 12

... Ambient Operating Temperature A T Temperature Under Bias BIAS T Storage Temperature STG T Lead Temperature During Soldering LEAD V Input or Output Voltage IO V Flash Memory Core Supply Voltage DDF V Input/Output Supply Voltage DDQ V SRAM Supply Voltage DDS V Flash Memory Program Voltage PPF I Output Short Circuit Current O t ...

Page 13

... C Input Capacitance IN C Output Capacitance OUT Note: Sampled only, not 100% tested. M36W0R5020T0, M36W0R5020B0 Conditions summarized in AC Measurement check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Flash Memory Min Max 1.7 1.95 – – 1.7 1.95 11.4 12.6 V +0.4 –0.4 DDQ – ...

Page 14

... M36W0R5020T0, M36W0R5020B0 Table 6. Flash Memory DC Characteristics - Currents Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO Supply Current Asynchronous Read (f=6MHz) Supply Current Synchronous Read (f=54MHz) I DD1 Supply Current Synchronous Read (f=66MHz) I Supply Current (Reset) DD2 I Supply Current (Standby) DD3 I Supply Current (Automatic Standby) ...

Page 15

... Table 7. Flash Memory DC Characteristics - Voltages Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage Program Voltage-Logic PP1 PPF V V Program Voltage Factory PPH PPF V Program or Erase Lockout PPLK V V Lock Voltage LKO ...

Page 16

M36W0R5020T0, M36W0R5020B0 Figure 8. SRAM Read Mode AC Waveforms, Address Controlled with UB A0-A17 DQ0-DQ15 DATA VALID Note Low High Low Figure 9. SRAM Read AC Waveforms, G A0-A17 E1 ...

Page 17

Table 9. SRAM Read AC Characteristics Symbol Alt t AVAV t t Read Cycle Time E1LE1H RC t E2HE2L t t Address Valid to Output Valid AVQV Address Transition to Output Transition AVQX OHA (2) t Byte ...

Page 18

M36W0R5020T0, M36W0R5020B0 Figure 11. SRAM Write AC Waveforms, E1 A0-A17 tGHDZ DQ0-DQ15 Note and UB ,LB must be asserted to initiate ...

Page 19

Figure 12. SRAM Write AC Waveforms, W A0-A17 tGHDX DQ0-DQ15 Note and UB ,LB must be asserted to initiate a write ...

Page 20

M36W0R5020T0, M36W0R5020B0 Figure 13. SRAM Write AC Waveforms, W A0-A17 DQ0-DQ15 Note: 1. During this period, the I/O pins are in output mode and input signals should not be ...

Page 21

Table 10. SRAM Write AC Characteristics Symbol Alt t t Write Cycle Time AVAV AVE1L t , AVE2H t Address Valid to Beginning of Write SA t AVWL t AVBL t AVWH t AVE1H t Address Valid ...

Page 22

M36W0R5020T0, M36W0R5020B0 Figure 15. SRAM Low V DDS V DDS Figure 16. SRAM Low V DDS V DDS Table 11. SRAM Low V Data Retention Characteristic DDS Symbol Parameter ...

Page 23

PACKAGE MECHANICAL Figure 17. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Outline BALL "A1" FE Note: Drawing is not to scale. Table 12. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, ...

Page 24

... E = Lead-free and RoHS Package, Standard Packing F = Lead-free and RoHS Package, Tape & Reel Packing Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available op- tions (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST- Microelectronics Sales Office nearest to you ...

Page 25

... Date Version 27-Aug-2003 1.0 First Issue M36W0R5030T0 and M36W0R5030B0 part numbers and 8 Mbit SRAM option removed. 0.15µm Flash memory technology replaced by the 0.13µm technology. 06-May-2004 2.0 Package specifications updated. E and F Lead-free Package options added to 13., Ordering Information Document status promoted to full Datasheet. 17-Dec-2004 3 ...

Page 26

M36W0R5020T0, M36W0R5020B0 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from ...

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