M58LW032 STMICROELECTRONICS [STMicroelectronics], M58LW032 Datasheet - Page 14

• Manufacturer Part Number: M58LW032
• Description: 32 Mbit 2Mb x16, Uniform Block, Burst 3V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M58LW032A
put Enable must remain High, V
whole Asynchronous Bus Write operation. See
Figures 15 and 17 Asynchronous Latch Controlled
Write AC Waveforms, and Tables 18 and 19,
Asynchronous Write and Latch Controlled Write
AC Characteristics, for details of the timing re-
quirements.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when the Output Enable
is High.
Standby. When Chip Enable is High, V
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high imped-
ance state regardless of Output Enable or Write
Enable. The Supply Current is reduced to the
Standby Supply Current, I
During Program or Erase operations the memory
will continue to use the Program/Erase Supply
Table 2. Asynchronous Bus Operations
Note: 1. X = Don’t Care V
14/61
Asynchronous Bus Read
Asynchronous Latch
Controlled Bus Read
Asynchronous Page Read
Asynchronous Bus Write
Asynchronous Latch
Controlled Bus Write
Output Disable
Standby
Power-Down
Bus Operation
IL
or V
IH
DD1
. High = V
Address Latch
Read
Address Latch
.
IH
Step
IH
or V
, during the
HH
.
IH
, the
V
V
V
V
V
V
V
V
E
X
IH
IL
IL
IL
IL
IL
IL
IL
Current, I
til the operation completes.
Automatic Low Power. If there is no change in
the state of the bus for a short period of time during
Asynchronous Bus Read operations the memory
enters Auto Low Power mode where the internal
Supply Current is reduced to the Auto-Standby
Supply Current, I
still output data if a Bus Read operation is in
progress.
Automatic Low Power is only available in Asyn-
chronous Read modes.
Power-Down. The memory is in Power-Down
mode when Reset/Power-Down, RP, is Low. The
power consumption is reduced to the Power-Down
level, I
independent of Chip Enable, Output Enable or
Write Enable.
V
V
V
V
V
V
V
G
X
X
IH
IH
IH
IL
IL
IL
IL
V
V
V
V
V
V
V
DD2
W
X
X
IH
IH
IH
IH
IH
IL
IL
DD3
, and the outputs are high impedance,
High
High
High
High
High
High
High
High
RP
V
, for Program or Erase operations un-
IL
DD5
V
V
V
V
V
V
X
X
X
L
IH
. The Data Inputs/Outputs will
IL
IL
IL
IL
IL
Address
Address
Address
Address
Address
A1-A21
X
X
X
X
Data Output
Data Output
Data Output
DQ0-DQ15
Data Input
Data Input
High Z
High Z
High Z
High Z