HYB39S256160DTL-8

Manufacturer Part NumberHYB39S256160DTL-8
Description256-MBit Synchronous DRAM
ManufacturerINFINEON [Infineon Technologies AG]
HYB39S256160DTL-8 datasheet
 
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D a t a S h e e t , R e v . 1 . 0 2 , F e b . 2 0 0 4
H Y B 3 9 S 2 5 6 4 0 0 D [ C / T ] ( L )
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HYB39S256160DTL-8 Summary of contents

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    Edition 2004-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2004. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of ...

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    ... Memory Products ...

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    HYB39S256[40/80/16]0D[C/T](L) Revision History: Rev. 1.02 Page Subjects (major changes since last revision) 17 Corrected Mode Register Definition in chapter 3 all Various layout and editorial changes Previous Version: Rev. 1.01 all Various layout and editorial changes Previous Version: Rev. 1.0 ...

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    Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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    ... All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device ...

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    ... HYB 39S256160DT-6 PC166-333-520 HYB 39S256160DT-7 PC133-222-520 HYB 39S256160DT-7.5 PC133-333-520 HYB 39S256160DT-8 PC100-222-620 HYB39S256400DTL-x – HYB39S256800DTL-x – HYB39S256160DTL-x – HYB39S256xx0DC(L)-x – Data Sheet HYB39S256[40/80/16]0D[C/T](L) 256-MBit Synchronous DRAM Package Description P-TSOP-54-2 (400mil) 166MHz 4B x 16M x 4 SDRAM P-TSOP-54-2 (400mil) 143MHz 4B x 16M x 4 SDRAM ...

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    Pin Configuration 2.1 Signal Pin Description Table 3 Signal Pin Description Pin Type Signal Polarity Function CLK Input Pulse Positive Edge CKE Input Level Active High CS Input Pulse Active Low RAS Input Pulse Active CAS Low WE A0 ...

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    Table 3 Signal Pin Description Pin Type Signal Polarity Function V V Supply – – Supply – – DDQ SSQ NC – – – 2.2 Package P–TSOPII– DQ0 V DDQ DQ1 DQ2 V SSQ ...

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    Package P–TFBGA–54 Table 4 Pin Configuration for x16 devices DQ15 V SS SSQ DQ14 DQ13 V DDQ DQ12 DQ11 V SSQ DQ10 DQ9 V DDQ V DQ8 REF A12 A11 A9 ...

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    Block Diagrams rray B a ...

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    ... Array Bank 1 Bank 2 8192 8192 x 1024 x 1024 x 8 Bit x 8 Bit Output Buffer DQ0 - DQ7 12 HYB39S256[40/80/16]0D[C/T](L) 256-MBit Synchronous DRAM Pin Configuration Refresh Counter Row Decoder Memory Array Bank 3 8192 x 1024 x 8 Bit Control Logic & Timing Generator SPB04128 Rev. 1.02, 2004-02 10072003-13LE-FGQQ ...

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    ... Array Bank 1 Bank 2 8192 x 512 8192 x 512 x 16 Bit x 16 Bit Output Buffer DQ0 - DQ15 13 HYB39S256[40/80/16]0D[C/T](L) 256-MBit Synchronous DRAM Pin Configuration Refresh Counter Row Decoder Memory Array Bank 3 8192 x 512 x 16 Bit Control Logic & Timing Generator SPB04129 Rev. 1.02, 2004-02 10072003-13LE-FGQQ ...

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    Functional Description 3.1 Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the truth table for the operation ...

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    Initialization The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the ...

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    MR Mode Register Definition BA1 BA0 A12 A11 A10 0 0 reg. addr Field Bits Type Description BL [2:0] w Burst Length Number of sequential bits per DQ related to one read/write command, see Chapter 3.3.1 Note: All other bit ...

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    Burst Length Table 8 Burst Length and Sequence Burst Length Starting Column Address FullPage ...

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    ... If a Burst Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory. 3.5 Operations 3 ...

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    Full page burst operation is only possible using the sequential burst type and page length is a function of the I/O organization and column addressing. Full page burst operation does not self terminate once the burst length has been reached. ...

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    Electrical Characteristics 4.1 Operating Conditions Table 10 Absolute Maximum Ratings Parameter Input / Output voltage relative to V Voltage on supply relative to DD Voltage on V supply relative to DDQ Operating Temperature Storage temperature range Power dissipation per ...

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    Table 12 Input and Output Capacitances Parameter Input Capacitances: CK, CK Input Capacitance (A0-A12, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM) Input/Output Capacitance (DQ °C; VDD,VDDQ = 3.3 V ± 0 ...

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    I Table 14 Specifications and Conditions DD Symbol DD1 RC RC(min CKE ≤ DD2P IH (min.) IL(max CKE≥ V ...

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    AC Characteristics Table 15 AC Timing - Absolute Specifications –8/-7.5/–7/-6 Parameter Clock and Clock Enable Clock Cycle Time CAS Latency = 3 CAS Latency = 2 Clock Frequency CAS Latency = 3 CAS Latency = 2 Access Time from ...

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    Table 15 AC Timing - Absolute Specifications –8/-7.5/–7/-6 (cont’d) Parameter Refresh Cycle Refresh Period (8192 cycles) Self Refresh Exit Time Data Out Hold Time Read Cycle Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data ...

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    Figure 5 Measurement conditions for Data ...

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    Package Outlines Plastic Package P-TSOPII-54 (400 mil, 0.8 mm lead pitch) Thin Small Outline Package, SMD 0.8 3) +0.1 0.35 -0.05 54 Index Marking 1) Does not include plastic or metal protrusion of 0.15 max per side 2) Does ...

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    TFBGA-54 package ( mm, 54 balls) Figure 7 Package Outline TFBGA-54 Data Sheet HYB39S256[40/80/16]0D[C/T](L) 256-MBit Synchronous DRAM 27 Package Outlines Rev. 1.02, 2004-02 10072003-13LE-FGQQ ...

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    Published by Infineon Technologies AG ...