HYB18T512160AF-3 QIMONDA [Qimonda AG], HYB18T512160AF-3 Datasheet
HYB18T512160AF-3
Related parts for HYB18T512160AF-3
HYB18T512160AF-3 Summary of contents
Page 1
...
Page 2
... HYB18T512400AF(L), HYB18T512800AF(L), HYB18T512160AF(L) Revision History: 2007-01, Rev. 1.71 Page Subjects (major changes since last revision) All Qimonda update All Adapted internet edition 108 Modified AC Timing Parameters Previous Revision: 2006-05, Rev. 1.7 57 Changed “Read” to “Write” in condition 4. 57 Removed text “Maximum power up interval for As 20.0 ms. The power interval is defined as the amount of time it takes for to 1.8 V ± ...
Page 3
Overview This chapter gives an overview of the 512-Mbit DDR2 SDRAM product family and describes its main characteristics. 1.1 Features The 512-Mbit DDR2 SDRAM offers the following key features: • 1.8 V ± 0.1 V Power Supply 1.8 V ...
Page 4
Product Type Speed Code Speed Grade Max. Clock Frequency Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time Product Type Speed Code Speed Grade Max. Clock Frequency Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row ...
Page 5
Description The 512-Mbit DDR2 DRAM is a high-speed Double-Data- Rate-Two CMOS Synchronous DRAM device containing 536,870,912 bits and internally configured as a quad-bank DRAM. The 512-Mbit device is organized as either 32 Mbit × 4 I/O × 4 banks, ...
Page 6
... HYB18T512800AF–3 ×16 HYB18T512160AF–3 ×4 HYB18T512400AF–3S ×8 HYB18T512800AF–3S ×16 HYB18T512160AF–3S 1) CAS: Column Adress Strobe 2) RCD: Row Column Delay 3) RP: Row Precharge Note: For product nomenclature see Chapter 9 Rev. 1.71, 2007-01 03062006-CPCN-4867 HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5] Ordering Information for RoHS compliant products ...
Page 7
Pin Configuration This chapter contains the pin configuration. 2.1 Pin Configuration for TFBGA–60 TFBGA–84 The pin configuration of a DDR2 SDRAM is listed by function in columns are explained in Table 7 and Table 8 for × 4, for ...
Page 8
Pin# Name Pin Type A10 ...
Page 9
Pin# Name Pin Type D1 DQ4 I/O D9 DQ5 I/O B1 DQ6 I/O B9 DQ7 I/O Data Signals ×16 organization G8 DQ0 I/O G2 DQ1 I/O H7 DQ2 I/O H3 DQ3 I/O H1 DQ4 I/O H9 DQ5 I/O F1 DQ6 ...
Page 10
Pin# Name Pin Type V A1 PWR DD V A7,B2,B8,D2,D PWR SSQ 8 V A3,E3 PWR SS Power Supplies ×4/×8 organizations REF V E1 PWR DDL V E9,H9,L1 PWR PWR SSDL V J1,K9 PWR ...
Page 11
Abbreviation Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I bidirectional input/output signal. AI Input. Analog levels. PWR Power GND Ground NC Not Connected Abbreviation Description SSTL Serial Stub Terminated Logic (SSTL_18) LV-CMOS Low ...
Page 12
TFBGA Ball Out Diagrams This chapter contains the TFBGA Ball Out Diagrams. Notes and are power and ground for the DLL. DDL SSDL V V connected to on the device and are isolated ...
Page 13
Notes 1. RDQS / RDQS are enabled by EMRS(1) command RDQS / RDQS is enabled, the DM function is disabled 3. When enabled, RDQS & RDQS are used as strobe signals during reads. Rev. 1.71, 2007-01 03062006-CPCN-4867 HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5] ...
Page 14
Notes 1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is data strobe for DQ[7:0] Rev. 1.71, 2007-01 03062006-CPCN-4867 HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5] Pin Configuration for × 16 components, PG-TFBGA-84-8 2. LDM is the data mask signal for DQ[7:0], UDM is the data mask ...
Page 15
Mbit DDR2 Addressing This chapter contents the table for the 512 Mbit DDR2 Addressing. Configuration Bank Address Number of Banks Auto-Precharge Row Address Column Address Number of Column Address Bits Number of I/Os Page Size [Bytes] 1) Referred ...
Page 16
Configuration Bank Address Number of Banks Auto-Precharge Row Address Column Address Number of Column Address Bits Number of I/Os Page Size [Bytes] 1) Referred to as ’org’ 2) Referred to as ’colbits’ colbits × org/8 [Bytes] 3) PageSize = 2 ...
Page 17
Functional Description 1) Field Bits Type Description BA2 16 reg. addr. Bank Address [2] Note: BA2 not available on 256 Mbit and 512 Mbit components 0 B BA1 15 Bank Address [ BA0 14 Bank Address [0] ...
Page 18
Field Bits Type Description CL [6:4] w CAS Latency Note: All other bit combinations are illegal. 011 B 100 B 101 B 110 B 111 Burst Type [2:0] w Burst ...
Page 19
Field Bits Type Description BA2 16 reg. addr. Bank Address [2] Note: BA2 not available on 256 Mbit and 512 Mbit components 0 B BA1 15 Bank Address [ BA0 14 Bank Address [ A13 ...
Page 20
Field Bits Type Description AL [5:3] — Additive Latency Note: All other bit combinations are illegal. 000 B 001 B 010 B 011 B 100 B R 6,2 Nominal Termination Resistance of ODT TT Note: See ...
Page 21
EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010 1) Field Bits Type Description BA2 16 reg.addr Bank Address [2] Note: BA2 is not available on 256 Mbit and 512 Mbit components 0 BA2 Bank Address B BA1 15 Bank Adress [1] ...
Page 22
EMR(3) Programming Extended Mode Register Definition (BA[2:0]=010 1) Field Bits Type Description BA2 16 reg.addr Bank Address [2] Note: BA2 is not available on 256 Mbit and 512 Mbit components 0 BA2 Bank Address B BA1 15 Bank Adress [1] ...
Page 23
Input Pin ×4 components DQ[3:0] DQS DQS DM ×8 components DQ[7:0] DQS DQS RDQS RDQS DM ×16 components DQ[7:0] DQ[15:8] LDQS LDQS UDQS UDQS LDM UDM Note don’t care bit set to low bit ...
Page 24
Burst Length Starting Address (A2 A1 A0) × × ×1 0 × ...
Page 25
Truth Tables This chapter contains the truth tables. Function CKE Previous Cycle (Extended) Mode H Register Set Auto-Refresh H Self-Refresh Entry H Self-Refresh Exit L Single Bank Precharge H Precharge all Banks H Bank Activate H Write H Write ...
Page 26
Current State CKE Previous Cycle (N-1) Power-Down L L Self Refresh L L Bank(s) Active H All Banks Idle H H Any State other than H listed above 1) Current state is the state of the DDR2 SDRAM immediately ...
Page 27
AC & DC Operating Conditions This chapter contains the AC & DC Operating Conditions. 5.1 Absolute Maximum Ratings Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Symbol Parameter V V Voltage on ...
Page 28
DC Characteristics This chapter describes the DC characteristics. Symbol Parameter V Supply Voltage DD V Supply Voltage for DLL DDDL V Supply Voltage for Output DDQ V Input Reference Voltage REF V Termination Voltage ...
Page 29
DC & AC Characteristics DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The ...
Page 30
Symbol Condition V Input reference voltage REF V Input signal maximum peak to peak swing SWING.MAX SLEW Input signal minimum Slew Rate 1) Input waveform timing is referenced to the input signal crossing through the 2) The input signal minimum ...
Page 31
Symbol Parameter V DC input signal voltage IN(dc differential input voltage ID(dc differential input voltage ID(ac differential cross point input voltage IX(ac differential cross point output voltage 0.5 × OX(ac ...
Page 32
Output Buffer Characteristics This chapter describes the Output Buffer Characteristics. Symbol Parameter I Output Minimum Source DC Current OH I Output Minimum Sink DC Current 1 1. – ...
Page 33
Symbol Description — Output Impedance — Pull-up / Pull down mismatch — Output Impedance step size for OCD calibration S Output Slew Rate OUT Absolute Specifications ( ; = 1.8 V OPER DD meet timing, voltage and ...
Page 34
Overshoot and Undershoot Specification This chapter describes the Overshoot and Undershoot Specification. AC Overshoot / Undershoot Specification for Address and Control Pins Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area V Maximum ...
Page 35
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area V Maximum overshoot area above DDQ V Maximum undershoot area below SSQ AC ...
Page 36
Currents, Specifications,Conditions This chapter contains the currents, specifications and conditions. Parameter Operating Current - One bank Active - Precharge CK(IDD) RC RC(IDD) RAS RAS.MIN(IDD) and control inputs ...
Page 37
Parameter Self-Refresh Current CKE ≤ 0.2 V; external clock off, CK and Other control and address inputs are floating, Data bus inputs are floating. Operating Bank Interleave Read Current I 1. All banks interleaving reads, = ...
Page 38
Symbol –3 DDR2–667 Max DD0 DD1 110 I 50 DD2N I 5.5 DD2P I — DD2P( DD2Q I 50 DD3N I (MRS DD3P I (MRS DD3P I 130 DD4R ...
Page 39
Electrical Characteristics This chapter lists the electrical characteristics. 7.1 Speed Grade Definitions This chapter contains the speed grade definition tables. Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ ...
Page 40
Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time 1) Timings are guaranteed with CK/CK differential Slew ...
Page 41
AC Timing Parameters This chapter contains the AC timing parameters. Parameter DQ output access time from CAS to CAS command delay Average clock high pulse width Average clock period CKE minimum pulse width ( high and ...
Page 42
Parameter Average periodic refresh Interval 0°C ≤ T ≤ 85°C CASE 85°C ≤ T ≤ 95°C CASE Read preamble Read postamble Internal Read to Precharge command delay Write preamble Write postamble Write recovery time Internal write to read command delay ...
Page 43
Input waveform timing with differential data strobe enabled MR[bit10 referenced from the differential data strobe crosspoint the input signal crossing at the level for a falling signal and from the differential data ...
Page 44
Rev. 1.71, 2007-01 03062006-CPCN-4867 HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5] 512-Mbit DDR2 SDRAM Method for calculating transitions and endpoint Differential input waveform timing - Differential input waveform timing - 44 Internet Data Sheet FIGURE 8 FIGURE and DS DS FIGURE 10 t ...
Page 45
Parameter DQ output access time from CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks ...
Page 46
Parameter Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Precharge-All (8 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Active bank A to Active bank B ...
Page 47
The , and , parameters are referenced to a specific voltage level, which specify when the device output is no longer driving HZ RPST LZ RPRE begins ...
Page 48
Parameter DQS falling edge hold time from CK (write cycle) DQS falling edge to CK setup time (write cycle) Clock half period Data-out high-impedance time from Address and control input hold time Address and control input pulse ...
Page 49
Parameter Exit Self-Refresh to Read command Write recovery time for write with Auto- Precharge = 1.8 V ± 0 1.8 V ±0.1 V. See notes DDQ DD 2) Timing that is not specified is illegal ...
Page 50
ODT AC Electrical Characteristics This chapter contains the ODT AC electrical characteristics tables. Symbol Parameter / Condition t ODT turn-on delay AOND t ODT turn-on AON t ODT turn-on (Power-Down Modes) AONPD t ODT turn-off delay AOFD t ODT ...
Page 51
ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400 Symbol Parameter / Condition t ODT turn-on delay AOND t ODT turn-on AON t ODT turn-on (Power-Down Modes) AONPD t ODT turn-off delay AOFD t ODT turn-off AOF t ODT ...
Page 52
Package Dimensions This chapter contains the package dimensions. Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.71, 2007-01 03062006-CPCN-4867 HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5] 512-Mbit DDR2 SDRAM Package Outline PG-TFBGA-60 52 Internet Data Sheet ...
Page 53
Rev. 1.71, 2007-01 03062006-CPCN-4867 HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5] 512-Mbit DDR2 SDRAM Package Outline PG-TFBGA-84 53 Internet Data Sheet FIGURE 12 ...
Page 54
... Internet Data Sheet 512-Mbit DDR2 SDRAM TABLE 45 Nomenclature Fields and Examples –3.7 –– TABLE 46 DDR2 Memory Components Coding Constant SSTL_18 DDR2 256 M 512 × 4 × 8 × 16 look up table First Second Third FBGA, lead-containing FBGA, lead-free DDR2– ...
Page 55
List of Figures Pin Configuration for × 4 components, PG-TFBGA-60 (top view ...
Page 56
... DRAM Component Timing Parameter by Speed Grade - DDR2-400 Table 43 ODT AC Characteristics and Operating Conditions for DDR2-667 Table 44 ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . 51 Table 45 Nomenclature Fields and Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 46 DDR2 Memory Components Rev. 1.71, 2007-01 03062006-CPCN-4867 HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5] 512-Mbit DDR2 SDRAM ) . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 57
Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 58
Edition 2007-01 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or ...