HYB18T512160BF QIMONDA [Qimonda AG], HYB18T512160BF Datasheet - Page 19

• Manufacturer Part Number: HYB18T512160BF
• Description: 200 Pin Small-Outlined DDR2 SDRAMs Modules
• Manufacturer: QIMONDA [Qimonda AG]

3.3.2
Timing Parameters for DDR2–800
Rev. 1.1, 2006-10
03292006-5LTN-QML0
Parameter
DQ output access time from CK / CK
DQS output access time from CK / CK
Average clock high pulse width
Average clock low pulse width
Average clock period
DQ and DM input setup time
DQ and DM input hold time
Control & address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK / CK
DQS/DQS low-impedance time from CK / CK
DQ low impedance time from CK/CK
DQS-DQ skew for DQS & associated DQ signals
CK half pulse width
DQ hold skew factor
DQ/DQS output hold time from DQS
Write command to DQS associated clock edges
DQS latching rising transition to associated clock
edges
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Write postamble
Write preamble
Address and control input setup time
Address and control input hold time
Read preamble
Read postamble
CAS to CAS command delay
Write recovery time
Auto-Precharge write recovery + precharge time
Internal write to read command delay
Component AC Timing Parameters
[Table
16], DDR2–667
DRAM Component Timing Parameter by Speed Grade - DDR2–800
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC
DQSCK
CH.AVG
CL.AVG
CK.AVG
DS.BASE
DH.BASE
IPW
DIPW
HZ
LZ.DQS
LZ.DQ
DQSQ
HP
QHS
QH
DQSS
DQSH
DQSL
DSS
DSH
WPST
WPRE
IS.BASE
IH.BASE
RPRE
RPST
CCD
WR
DAL
WTR
[Table
19
17], DDR2–533C
DDR2–800
–400
–350
0.48
0.48
2500
50
125
0.6
0.35
—
t
2 x
—
Min(
t
—
t
RL – 1
– 0.25
0.35
0.35
0.2
0.2
0.4
0.35
175
250
0.9
0.4
2
15
WR +
7.5
Min.
AC.MIN
CL.ABS
HP
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
–
t
AC.MIN
t
CH.ABS
t
)
QHS
t
nRP
,
[Table
+400
+350
0.52
0.52
8000
––
––
—
—
—
—
—
—
0.6
—
—
—
1.1
0.6
—
—
—
Max.
t
t
t
200
__
300
—
+ 0.25
—
AC.MAX
AC.MAX
AC.MAX
SO-DIMM DDR2 SDRAM Module
18] and DDR2–400
Unit
ps
ps
t
t
ps
ps
ps
t
t
ps
ps
ps
ps
ps
ps
ps
nCK
t
t
t
t
t
t
t
ps
ps
t
t
nCK
ns
nCK
ns
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
Internet Data Sheet
TABLE 16
Note
8)
9)
9)
10)11)
10)11)
10)11)
12)13)14)
13)14)15)
9)16)
9)16)
9)16)
17)
18)
19)
20)
21)
21)
21)
22)23)
23)24)
25)26)
25)27)
1)
28)29)
1)30)
[Table
1)2)3)4)5)6)7)
19]