STK15C68-SF25I SIMTEK [Simtek Corporation], STK15C68-SF25I Datasheet - Page 8

• Manufacturer Part Number: STK15C68-SF25I
• Description: 32Kx8 PowerStore nvSRAM
• Manufacturer: SIMTEK [Simtek Corporation]

STK15C88
Document Control #ML0016 Rev 0.3
The STK15C88 is a versatile memory chip that pro-
vides several modes of operation. The STK15C88
can operate as a standard 32K x 8
32K x 8 nonvolatile element shadow to which the
SRAM
SRAM
NOISE CONSIDERATIONS
Note that the STK15C88 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1μF connected between V
and V
possible. As with all high-speed
careful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK15C88 performs a
and G are low and W is high. The address specified
on pins A
bytes will be accessed. When the
by an address transition, the outputs will be valid
after a delay of t
initiated by E or G, the outputs will be valid at t
at t
outputs will repeatedly respond to address changes
within the t
sitions on any control input pins, and will remain valid
until another address change or until E or G is
brought high.
SRAM WRITE
A
low. The address inputs must be stable prior to
entering the
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ
ten into the memory if it is valid t
of a W controlled
E controlled
It is recommended that G be kept high during the
entire
the common I/O lines. If G is left low, internal cir-
cuitry will turn off the output buffers t
goes low.
WRITE
GLQV
February, 2007
SS
can be updated in nonvolatile mode.
, whichever is later (
WRITE
information can be copied, or from which the
, using leads and traces that are as short as
cycle is performed whenever E and W are
0-14
AVQV
WRITE
WRITE
determines which of the 32,768 data
cycle to avoid data bus contention on
access time without the need for tran-
AVQV
WRITE
.
(
cycle and must remain stable
READ
or t
READ
cycle #1). If the
READ
DVEH
before the end of an
cycle #2). The data
DVWH
CMOS
cycle whenever E
READ
nvSRAM OPERATION
SRAM
before the end
0-7
WLQZ
ICs, normal
will be writ-
is initiated
. It has a
READ
after W
ELQV
or
CC
is
8
SOFTWARE NONVOLATILE STORE
The STK15C88 software
executing sequential
address locations. During the
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the
nonvolatile memory. Once a
ated, further input and output are disabled until the
cycle is completed.
Because a sequence of
addresses is used for
tant that no other
vene in the sequence or the sequence will be
aborted and no
To initiate the software
READ
The software sequence must be clocked with E con-
trolled
Once the sixth address in the sequence has been
entered, the
chip will be disabled. It is important that
and not
although it is not necessary that G be low for the
sequence to be valid. After the t
been fulfilled, the
READ
SOFTWARE NONVOLATILE RECALL
A software
of
ware
the following sequence of
performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
READ
STORE
sequence must be performed:
and
READ
operations in a manner similar to the soft-
WRITE
WRITE
RECALL
s.
initiation. To initiate the
STORE
STORE
cycles be used in the sequence,
operation.
SRAM
READ
cycle is initiated with a sequence
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0FC0 (hex)
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0C63 (hex)
cycle will commence and the
READ
STORE
or
STORE
will again be activated for
STORE
or
RECALL
READ
cycles from six specific
WRITE
READ
STORE
STORE
initiation, it is impor-
cycle, the following
STORE
operations must be
cycle is initiated by
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
will take place.
s from specific
SRAM
accesses inter-
cycle an erase
cycle time has
RECALL
cycle is initi-
READ
data into
cycles
cycle,