E28F004BX-B120 INTEL [Intel Corporation], E28F004BX-B120 Datasheet
E28F004BX-B120
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E28F004BX-B120 Summary of contents
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... X 16 512K X 8) FLASH MEMORY FAMILY x8 x16 Input Output Architecture Y 28F400BX-T 28F400BX-B For High Performance and High Integration 16-bit and 32-bit CPUs x8-only Input Output Architecture Y 28F004BX-T 28F004BX-B For Space Constrained 8-bit Applications Upgradeable to Intel’s Smart Voltage Y Products ...
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... For very low power applications using supply refer to the Intel 28F400BL-T B 28F004BL-T B 4-Mbit Boot Block Flash Memory Family datasheet Manufactured on Intel’ micron ETOX III process the 4-Mbit flash memory family provides world class quality reliability and cost-effectiveness at the 4-Mbit density level ...
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... Main Features The 28F400BX 28F004BX boot block flash memory family is a very high performance 4-Mbit (4 194 304 bit) memory family organized as either 256 KWords (262 144 words bits each or 512 Kbytes (524 288 bytes bits each Seven Separately Erasable Blocks including a ...
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... Write State Machine (WSM) automatically executes the algorithms and timings necessary for program and erase operations including verifications there- by unburdening the microprocessor or microcontrol- ler Writing of memory data is performed in word or byte increments for the 28F400BX family and in byte increments for the 28F004BX family typically within 9 ...
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... B 28F004BX-T B This increase in software sophistication augments the probability that a code update will be required after the PC is shipped The 4-Mbit flash memory products provide an inexpensive update solution for the notebook and handheld personal computers while extending their product lifetime Furthermore the 4-Mbit flash memory products’ ...
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B 28F004BX-T B Figure 1 28F400BX Interface to Intel386 Figure 2 28F004BX Interface to INTEL 80C188EB 8-Bit Embedded Processor 6 290451 – Embedded Processor 290451 –24 ...
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... Figure 3 PSOP Lead Configuration for x8 x16 28F400BX 28F400BX-T B 28F004BX-T B The 28F004BX 40-Lead TSOP pinout shown in Fig- ure 5 is 100% compatible and provides a density upgrade for the 2-Mbit Boot Block flash memory or the 28F002BX 290451 – ...
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B 28F004BX-T B Figure 4 TSOP Lead Configuration for x8 x16 28F400BX Figure 5 TSOP Lead Configuration for x8 28F004BX 8 290451 – 3 290451 –20 ...
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... WSM is reset preventing any blocks from being programmed or erased therefore providing data protection during power transitions When RP transitions from logic low to logic high the flash memory enters the read-array mode OE I OUTPUT ENABLE Gates the device’ ...
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... Boot Block is locked the deep power-down mode is enabled and the WSM is reset preventing any blocks from being programmed or erased therefore providing data protection during power transitions When RP transitions from logic low to logic high the flash memory enters the read-array mode OE I OUTPUT ENABLE Gates the device’ ...
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WORD BYTE-WIDE PRODUCTS DESCRIPTION Figure 6 28F400BX Word Byte Block Diagram 28F400BX-T B 28F004BX ...
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... Main Block Operation Four main blocks of memory exist on the 28F400BX (3 x 128-Kbyte blocks and 1 x 96-Kbyte blocks) See the following section on Block Memory Map for the address location of these blocks for the 28F400BX-T and 28F400BX-B products 12 ...
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... The second 8-Kbyte pa- rameter block resides in memory space from 3C000H to 3CFFFH The 96-Kbyte main block re- sides in memory space from 30000H to 3BFFFH The three 128-Kbyte main blocks reside in memory space from 20000H to 2FFFFH 10000H to 1FFFFH and 00000H to 0FFFFH as shown below in Figure 8 28F400BX-T B 28F004BX-T B ...
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B 28F004BX 28F004BX PRODUCT DESCRIPTION Figure 9 28F004BX Byte-Wide Block Diagram 14 ...
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... B 28F004BX BLOCK MEMORY MAP Two versions of the 28F004BX product exist to sup- port two different memory maps of the array blocks in order to accommodate different microprocessor protocols for boot code location The 28F004BX-T memory map is inverted from the 28F004BX-B ...
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... The second 8-Kbyte pa- rameter block resides in memory space from 78000H to 79FFFH The 96-Kbyte main block re- sides in memory space from 60000H to 77FFFH The three 128-Kbyte main blocks reside in memory space from 40000H to 5FFFFH 20000H to 3FFFFH and 00000H to 1FFFFH ...
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Table 1 Bus Operations for WORD-WIDE Mode (BYTE Mode Notes Read 1 2 Output Disable Standby Deep Power-Down 9 Intelligent Identifier (Mfr Intelligent Identifier (Device Write Table 2 Bus Operations for BYTE-WIDE ...
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... minimum to valid data on the outputs READ ARRAY If the memory is not in the Read Array mode it is necessary to write the appropriate read mode com- mand to the CUI The 4-Mbit boot block flash family has three control functions all of which must be ...
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... PP Depending upon the application the system design- er may choose to make the V PP switchable available only when memory updates are desired The system designer can also choose to ‘‘hard-wire’’ 12V The 4-Mbit boot block PP flash family is designed to accommodate either de- ...
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B 28F004BX-T B Bus Command Cycles Req’d Read Array 1 Intelligent Identifier 3 Read Status Register 2 Clear Status Register 1 Erase Setup Erase Confirm 2 Word Byte Write Setup Write 2 Erase Suspend Erase Resume 2 Alternate Word ...
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Program Setup (40H or 10H) This command simply sets the CUI into a state such that the next write will load the address and data registers Either 40H or 10H can be used for Pro- gram Setup Both commands are ...
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... Programming of the memory results in specific bits within a byte or word being changed to a ‘‘0’’ If the user attempts to program ‘‘1’’s there will be no change of the memory cell content and no error oc- curs level The WSM PP has not been switched ...
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... The status register should be cleared before at- tempting the next operation Any CUI instruction can follow after erasure is completed however it must be recognized that reads from the memory array status register or Intelligent Identifier can not be ac- complished until the CUI is given the appropriate ...
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... The combination of low electric fields clean oxide pro- cessing and minimized oxide area per memory cell subjected to the tunneling electric field results in very high cycling capability ...
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Full Status Check Procedure 290451–7 Figure 12 Automated Byte Programming Flowchart 28F400BX-T B 28F004BX-T B Bus Command Comments Operation Write Setup Data 40H e Program Address Byte programmed Write Program Data to be programmed Address Byte ...
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B 28F004BX-T B Full Status Check Procedure Figure 13 Automated Word Programming Flowchart 26 Bus Command Operation Write Setup Program Write Program Read Standby Repeat for subsequent words Full status check can be done after each word or after ...
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Full Status Check Procedure 290451– 11 Figure 14 Automated Block Erase Flowchart 28F400BX-T B 28F004BX-T B Bus Command Comments Operation Write Setup Data 20H e Erase Address Within block erased Write Erase Data D0H e ...
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... STANDBY POWER at a logic- With logic-high level (V read mode the memory is placed in standby mode where the maximum I with CMOS input signals The standby operation dis- ables much of the device’s circuitry and substantially reduces device power consumption The outputs ...
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... PHQV During erase or program modes RP either erase or program operation The contents of the memory are no longer valid as the data has been corrupted by the RP function As in the read mode above all internal circuitry is turned off to achieve the current level ...
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B 28F004BX-T B ABSOLUTE MAXIMUM RATINGS Commercial Operating Temperature During Read During Block Erase and Word Byte Write Temperature Under Bias Extended Operating Temperature During Read During Block Erase and Word ...
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DC CHARACTERISTICS (Continued) Symbol Parameter I V Standby Current CCS Deep Powerdown Current CCD Read Current for CCR CC 28F400BX Word-Wide and Byte-Wide Mode and 28F004BX Byte-Wide Mode I V Word Byte Write Current ...
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B 28F004BX CHARACTERISTICS (Continued) Symbol Parameter V Output High Voltage (TTL) OH1 V Output High Voltage (CMOS) OH2 V V during Normal Operations PPL during Erase Write Operations PPH during Erase ...
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DC CHARACTERISTICS EXTENDED TEMPERATURE OPERATION Symbol Parameter I V Read Current for 28F400BX 1 5 CCR CC Word-Wide and Byte-Wide Mode 6 10 28F004BX Byte-Wide Mode I V Word Write Current CCW Block Erase Current CCE CC ...
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B 28F004BX CHARACTERISTICS EXTENDED TEMPERATURE OPERATION Symbol Parameter V Output High Voltage (CMOS) OH2 V V during Normal Operations PPL during Erase Write Operations PPH during Erase Write Operations PPH PP ...
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STANDARD TEST CONFIGURATION STANDARD AC INPUT OUTPUT REFERENCE WAVEFORM AC test inputs are driven for a logic ‘‘0’’ Input timing begins at V TTL ( Output timing ...
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B 28F004BX CHARACTERISTICS Read Only Operations Versions V 10 Symbol Parameter Notes t t Read Cycle Time AVAV Address to AVQV ACC Output Delay ...
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EXTENDED TEMPERATURE OPERATION AC CHARACTERISTICS Read Only Operations Versions Symbol Parameter t t Read Cycle Time AVAV Address to AVQV ACC Output Delay Output Delay ELQV High to PHQV ...
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B 28F004BX-T B Figure Waveforms for Read Operations 38 ...
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Figure 17 I (RMS) vs Frequency for x16 Operation e CC Figure 19 T ACC 28F400BX-T B 28F004BX-T B Figure 18 I (RMS) vs Frequency 5V) for x8 Operation e CC ...
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B 28F004BX-T B Figure 20 BYTE Timing Diagram for Both Read and Write Operations for 28F400BX 40 ...
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AC CHARACTERISTICS Versions V 10 Symbol Parameter Notes t t Write Cycle Time AVAV High PHWL PS Recovery to WE Going Low Setup to WE ELWL ...
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B 28F004BX CHARACTERISTICS WE 28F400BX- 28F004BX-60 Versions V 10 Symbol Parameter Notes Min Hold QVPH PHH HH from Valid SRD t Boot-Block 7 8 ...
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BLOCK ERASE AND WORD BYTE WRITE PERFORMANCE 10 28F400BX-60 28F004BX-60 Parameter Notes Min Boot Parameter 2 Block Erase Time Main Block 2 Erase Time Main Block Byte 2 Program Time Main Block Word 2 ...
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B 28F004BX-T B EXTENDED TEMPERATURE OPERATION AC CHARACTERISTICS WE Versions Symbol Parameter t Duration of Erase Operation WHQV3 (Parameter) t Duration of Erase Operation (Main) WHQV4 Hold from Valid SRD QVVL VPH ...
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Figure 21 AC Waveforms for a Write and Erase Operations (WE -Controlled Writes) 28F400BX-T B 28F004BX ...
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B 28F004BX CHARACTERISTICS CE -CONTROLLED WRITE OPERATIONS 28F400BX- 28F004BX-60 Versions V 10 Symbol Parameter Notes t t Write Cycle Time AVAV High PHEL PS Recovery to CE ...
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AC CHARACTERISTICS CE -CONTROLLED WRITE OPERATIONS 28F400BX- 28F004BX-60 Versions V 10 Symbol Parameter Notes Min t Input Rise Time IR t Input Fall Time IF NOTES 1 Chip-Enable Controlled Writes Write operations are driven ...
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B 28F004BX-T B Figure 22 Alternate A C Waveforms for Write and Erase Operations (CE -Controlled Writes) 48 ...
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... E28F004BX-T80 E28F004BX-B60 E28F004BX-B80 28F400BX-T B 28F004BX-T B Notes timing waveform) all set-up hold and inactive WE waveform TE28F400BX-T80 TB28F400BX-T80 TE28F400BX-B80 TB28F400BX-B80 TE28F004BX-T80 E28F004BX-T120 TE28F004BX-B80 E28F004BX-B120 (1 9) (Continued) (10) T28F400BX-80 (10) T28F004BX-80 Unit Min Max ...
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... AP-363 ‘‘Extended Flash BIOS Concepts for Portable Computers’’ 292148 AP-604 ‘‘Using Intel’s Boot Block Flash Memory Parameter Blocks to Replace EEPROM’’ 292178 AP-623 ‘‘Multi-Site Layout Planning Using Intel’s Boot Block Flash Memory’’ ...