CS5231-3GDF8 ONSEMI [ON Semiconductor], CS5231-3GDF8 Datasheet

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CS5231-3GDF8

Manufacturer Part Number
CS5231-3GDF8
Description
500 mA, 3.3 V Linear Regulator with Auxiliary Control
Manufacturer
ONSEMI [ON Semiconductor]
Datasheets

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CS5231-3GDF8
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ON Semiconductor
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CS5231−3
500 mA, 3.3 V Linear
Regulator with Auxiliary
Control
circuitry controlling an external PFET transistor thus managing two
input supplies. The part provides a 3.3 V regulated output either from
the main 5.0 V supply or a 3.3 V auxiliary that switches on when the
5.0 V supply is not present. This delivers constant, uninterrupted
power to the load. The CS5231−3 meets Intel’s “Instantly Available”
power requirements which follows from the “Advanced Configuration
and Power Interface” (ACPI) standards developed by Intel, Microsoft
and Toshiba.
500 mA with an overall accuracy of 2.0%. The internal NPN−PNP
composite pass transistor provides a low dropout voltage and requires
less supply current than a straight PNP design. Full protection with
both current limit and thermal shutdown is provided.
from flowing from V
input voltage is lower than the output voltage.
Network Interface Card (NIC). When the system enters a Sleep State
and the 5.0 V input drops below 4.4 V, the AuxDrv control signal on the
CS5231−3 is activated turning on the external PFET. This switches the
supply source from the 5.0 V input to the 3.3 V input through the PFET,
guaranteeing a constant 3.3 V output to the ASIC that is “glitch free.”
(TO263) package and the SOIC−8 4−Lead−fused (DF) package. Other
applications include desktop computers, power supplies with multiple
input sources and PCMCIA/PCI interface cards.
Features
January, 2004 − Rev. 5
The CS5231−3 combines a three−terminal linear regulator with
The CS5231−3 linear regulator provides a fixed 3.3 V output at
Designed for low reverse current, the IC prevents excessive current
The CS5231−3 can be used to provide power to an ASIC on a PCI
The CS5231−3 is available in two package types: the D
Linear Regulator
System Power Management
Internally Fused Leads in SOIC−8 Package
Semiconductor Components Industries, LLC, 2004
3.3 V 2.0% Output Voltage
3.0 mA Quiescent Current @ 500 mA
Fast Transient Response
Current Limit Protection
Thermal Shutdown with Hysteresis
450 mA Reverse Output Current
Auxiliary Supply Control
“Glitch Free” Transition Between Two Supplies
OUT
to either V
IN
or ground when the regulator
1
2
PAK−5
CS5231−3GDF8
CS5231−3GDFR8
CS5231−3GDP5
CS5231−3GDPR5
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1
Device
ORDERING INFORMATION
5
CS5231−3
1
PIN CONNECTIONS AND
AWLYWW
D
A
WL, L
YY, Y
WW, W = Work Week
8
GND
GND
MARKING DIAGRAMS
2
V
NC
PAK−5
http://onsemi.com
IN
1
1
= Assembly Location
= Wafer Lot
= Year
Package
D
D
SOIC−8
SOIC−8
SOIC−8
2
2
PAK−5
PAK−5
Publication Order Number:
Pin 1. No Connect
DF SUFFIX
CASE 751
CASE 936AC
SOIC−8
DP SUFFIX
8
D
2500 Tape & Reel
2. V
3. GND
4. V
5. AuxDrv
Tab = GND
750 Tape & Reel
2
AuxDrv
GND
GND
V
PAK−5
95 Units/Rail
50 Units/Rail
OUT
Shipping†
IN
OUT
CS5231−3/D

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CS5231-3GDF8 Summary of contents

Page 1

... V OUT input voltage is lower than the output voltage. The CS5231−3 can be used to provide power to an ASIC on a PCI Network Interface Card (NIC). When the system enters a Sleep State and the 5.0 V input drops below 4.4 V, the AuxDrv control signal on the CS5231−3 is activated turning on the external PFET. This switches the supply source from the 5.0 V input to the 3.3 V input through the PFET, guaranteeing a constant 3.3 V output to the ASIC that is “ ...

Page 2

... ESD Damage Threshold (Human Body Model second maximum above 183 C. *The maximum package power dissipation must be observed. ABSOLUTE MAXIMUM RATINGS Pin Name Pin Symbol IC Power Input Output Voltage Auxiliary Drive Output AuxDrv IC Ground CS5231−3 Internal Bias − Error + V UV Amp IN - ...

Page 3

... Guaranteed by design, not 100% production tested. Thermal shutdown is 100% functionally tested at wafer probe. Package Lead # 2 D PAK−5 SOIC− Tab CS5231− < T < < T < 125 C; 4. Test Conditions < 500 mA. OUT = 10mA 500 mA OUT = 10 mA ...

Page 4

... C 0.0 0.0 0.2 I (A) OUT Figure 4. Load Regulation vs. I Temperature 0.0 0.2 0.4 0.6 I (A) OUT Figure 6. V vs. I Over Junction OUT OUT Temperature CS5231−3 1.2 1.0 0.8 0.6 0.4 0.2 0 100 120 0 Figure 3. Line Regulation vs. I 390 380 370 360 0 0.4 Over Figure 5. Reverse Current vs. Junction OUT 4.52 125 C 4. ...

Page 5

... Stable Region 100 10 0.4 0 1.0 Figure 9. Region of Stable Operation 3.4 3.3 3.2 500 10 100 120 140 Figure 11. Transient Response OUT CS5231−3 GND AuxDrv indicates PFET body diode Figure 12. Application Circuit http://onsemi.com 5 2.0 3.0 4.0 5.0 6.0 7.0 Capacitance ESR ( ...

Page 6

... THEORY OF OPERATION The CS5231− fixed 3.3 V linear regulator that contains an auxiliary drive control feature. When V greater than the typical 4.5 V threshold, the IC functions as a linear regulator. It provides up to 500 mA of current to a load through a composite PNP−NPN pass transistor. An output capacitor greater than 10 mF with equivalent series resistance less than 1 ...

Page 7

... OUT V AUXDRV I = 375 3.465 OUT AUX Figure 18. Power−Up 3.465 V. I AUX is Compensated By Higher Value of V CS5231− OUT V AUXDRV Figure 19. Power−Down, V STABILITY CONSIDERATIONS and 3.3 is AUX The output capacitor helps determine three main characteristics of a linear regulator: startup, transient response and stability ...

Page 8

... R due to temperature. DS(ON not possible to remotely sense the output voltage of the CS5231−3 since the feedback path to the error amplifier is not externally available important to minimize results voltage drops due to metal resistance of high current PC OUT board traces ...

Page 9

... T J(MAX A(MAX Maximum ambient temperature and power dissipation are determined by the design, while q JA package manufacturer. The maximum junction temperature for operation of the CS5231−3 within specification is 150 C. The maximum power dissipation of a linear regulator is given as P D(MAX IN(MAX OUT(MIN LOAD(MAX IN(MAX) ) ...

Page 10

... The CS5231−3 power supply management solution is implemented in an area less than 1.5 square inches. Due to the simplicity of the design, output current must be derated if the CS5231−3 is operated at V voltages greater than 7.0 V. Figure 21 provides the derating curve on a maximum power dissipation if heatsink is added. ...

Page 11

... V tantalum capacitors C1 p−channel FET transistor U1 Linear regulator with auxiliary T1−T6 Turret pins CS5231−3 Temperature Performance The graph below shows thermal performance for the CS5231−3 across the normal operating output current range Figure 25 ...

Page 12

... PACKAGE DIMENSIONS CASE 936AC−01 2 For D PAK Outline and Dimensions − Contact Factory http://onsemi.com CS5231− PAK−5 DP SUFFIX ISSUE O 12 ...

Page 13

... G C SEATING PLANE −Z− 0.25 (0.010 PACKAGE THERMAL DATA Parameter R qJC R qJA *Depending on thermal properties of substrate. R CS5231−3 PACKAGE DIMENSIONS SOIC−8 DF SUFFIX CASE 751−07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT 1.52 0.060 7.0 4.0 0.275 ...

Page 14

... Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 14 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. CS5231−3/D ...

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