AT32UC3L064_11 ATMEL [ATMEL Corporation], AT32UC3L064_11 Datasheet - Page 91

• Manufacturer Part Number: AT32UC3L064_11
• Description: 32-bit Atmel AVR Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

10.4.3
10.4.4
32099HS–12/2011
FLASHCDW
SAU
2. Transfer error will stall a transmit peripheral handshake interface
3. VERSION register reads 0x120
1. Fuse Programming
2. Chip Erase
3. Wait 500 ns before reading from the flash after switching read mode
4. Flash self programming may fail in one wait state mode
5. VERSION register reads 0x100
1. The SR.IDLE bit reads as zero
If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral
handshake of the active channel will stall and the PDCA will not do any more transfers on
the affected peripheral handshake interface.
Fix/Workaround
Disable and then enable the peripheral after the transfer error.
The VERSION register reads 0x120 instead of 0x122.
Fix/Workaround
None.
Programming fuses does not work.
Fix/Workaround
Do not program fuses. All fuses will be erased during chip erase command.
When performing a chip erase, the device may report that it is protected (IR=0x11) and that
the erase failed, even if it was successful.
Fix/Workaround
Perform a reset before any further read and programming.
After switching between normal read mode and high-speed read mode, the application must
wait at least 500ns before attempting any access to the flash.
Fix/Workaround
Solution 1: Make sure that the appropriate instructions are executed from RAM, and that a
waiting-loop is executed from RAM waiting 500ns or more before executing from flash.
Solution 2. Execute from flash with a clock with period longer than 500ns. This guarantees
that no new read access is attempted before the flash has had time to settle in the new read
mode.
Writes in flash and user pages may fail if executing code is located in address space
mapped to flash, and the flash controller is configured in one wait state mode (the Flash
Wait State bit in the Flash Control Register (FCR.FWS) is one).
Fix/Workaround
Solution 1: Configure the flash controller in zero wait state mode (FCR.FWS=0).
Solution 2: Configure the HMATRIX master 1 (CPU Instruction) to use the unlimited burst
length transfer mode (MCFG1.ULBT=0), and the HMATRIX slave 0 (FLASHCDW) to use
the maximum slot cycle limit (SCFG0.SLOT_CYCLE=255).
The VERSION register reads 0x100 instead of 0x102.
Fix/Workaround
None.
The IDLE bit in the Status Register (SR.IDLE) reads as zero.
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