AT32UC3L064_11 ATMEL [ATMEL Corporation], AT32UC3L064_11 Datasheet - Page 95

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AT32UC3L064_11

Manufacturer Part Number
AT32UC3L064_11
Description
32-bit Atmel AVR Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
32099HS–12/2011
11. DFLLIF might lose fine lock when dithering is disabled
12. GCLK5 is non-functional
13. BRIFA is non-functional
14. SCIF VERSION register reads 0x100
15. BODVERSION register reads 0x100
16. DFLLVERSION register reads 0x200
17. RCCRVERSION register reads 0x100
18. OSC32VERSION register reads 0x100
19. VREGVERSION register reads 0x100
20. RC120MVERSION register reads 0x100
The DFLLIF dithering does not work.
Fix/Workaround
None.
When dithering is disabled and fine lock has been acquired, the DFLL might lose the fine
lock resulting in up to 20% over-/undershoot.
Fix/Workaround
Solution 1: When the DFLL is used as main clock source, the target frequency of the DFLL
should be 20% below the maximum operating frequency of the CPU. Don’t use the DFLL as
clock source for frequency sensitive applications.
Solution 2: Do not use the DFLL in closed loop mode.
GCLK5 is non-functional.
Fix/Workaround
None.
BRIFA is non-functional.
Fix/Workaround
None.
SCIFVERSION register reads 0x100 instead of 0x102.
Fix/Workaround
None.
BODVERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
DFLLVERSION register reads 0x200 instead of 0x201.
Fix/Workaround
None.
RCCRVERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
OSC32VERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
VREGVERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
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