P89LV51RD2BA PHILIPS [NXP Semiconductors], P89LV51RD2BA Datasheet - Page 59

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P89LV51RD2BA

Manufacturer Part Number
P89LV51RD2BA
Description
8-bit 80C51 3 V low power 64 kB Flash microcontroller with 1 kB RAM
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheets

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Product data
7.11.1 Idle mode
7.11.2 Power-down mode
Idle mode is entered setting the IDL bit in the PCON register. In idle mode, the program
counter (PC) is stopped. The system clock continues to run and all interrupts and peripherals
remain active. The on-chip RAM and the special function registers hold their data during this
mode.
The device exits idle mode through either a system interrupt or a hardware reset. Exiting idle
mode via system interrupt, the start of the interrupt clears the IDL bit and exits idle mode.
After exit the Interrupt Service Routine, the interrupted program resumes execution
beginning at the instruction immediately following the instruction which invoked the idle
mode. A hardware reset starts the device similar to a power-on reset.
The Power-down mode is entered by setting the PD bit in the PCON register. In the
Power-down mode, the clock is stopped and external interrupts are active for level
sensitive interrupts only. SRAM contents are retained during Power-down, the
minimum V
The device exits Power-down mode through either an enabled external level sensitive
interrupt or a hardware reset. The start of the interrupt clears the PD bit and exits
Power-down. Holding the external interrupt pin low restarts the oscillator, the signal
must hold low at least 1024 clock cycles before bringing back high to complete the
exit. Upon interrupt signal restored to logic V
execution resumes beginning at the instruction immediately following the instruction
which invoked Power-down mode. A hardware reset starts the device similar to
power-on reset.
To exit properly out of Power-down, the reset or external interrupt should not be
executed before the V
hold V
and stabilize (normally less than 10 ms).
DD
voltage long enough at its normal operating level for the oscillator to restart
DD
level is 2.0 V.
Rev. 04 — 02 December 2004
DD
line is restored to its normal operating voltage. Be sure to
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
IH
, the interrupt service routine program
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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