LPC2917/01 NXP [NXP Semiconductors], LPC2917/01 Datasheet

LPC2917/01

Manufacturer Part Number

LPC2917/01

Description

ARM9 microcontroller with CAN and LIN

Manufacturer

NXP [NXP Semiconductors]

Datasheet

1.LPC291701.pdf (86 pages)

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1. General description

2. Features

The LPC2917/2919/01 combine an ARM968E-S CPU core with two integrated TCM

blocks operating at frequencies of up to 125 MHz, CAN and LIN, 56 kB SRAM, up to

768 kB ﬂash memory, external memory interface, two 10-bit ADCs, and multiple serial and

parallel interfaces in a single chip targeted at consumer, industrial, medical, and

communication markets. To optimize system power consumption, the LPC2917/2919/01

has a very ﬂexible Clock Generation Unit (CGU) that provides dynamic clock gating and

scaling.

LPC2917/2919/01

ARM9 microcontroller with CAN and LIN

Rev. 02 — 17 June 2009

ARM968E-S processor running at frequencies of up to 125 MHz maximum.

Multi-layer AHB system bus at 125 MHz with three separate layers.

On-chip memory:

Dual-master, eight-channel GPDMA controller on the AHB multi-layer matrix which can

be used with the SPI interfaces and the UARTs, as well as for memory-to-memory

transfers including the TCM memories.

External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data

bus; up to 24-bit address bus.

Serial interfaces:

Two Tightly Coupled Memories (TCM), 16 kB Instruction TCM (ITCM), 16 kB Data

TCM (DTCM).

Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and 16 kB

SRAM.

8 kB ETB SRAM also available for code execution and data.

Up to 768 kB high-speed ﬂash-program memory.

16 kB true EEPROM, byte-erasable and programmable.

Two-channel CAN controller supporting FullCAN and extensive message ﬁltering

Two LIN master controllers with full hardware support for LIN communication. The

LIN interface can be conﬁgured as UART to provide two additional UART

interfaces.

Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support, and

RS485/EIA-485 (9 bit) support.

Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep;

Tx FIFO and Rx FIFO.

Two I

C-bus interfaces.

Preliminary data sheet

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