STR910FM32X6T STMICROELECTRONICS [STMicroelectronics], STR910FM32X6T Datasheet
STR910FM32X6T
Related parts for STR910FM32X6T
STR910FM32X6T Summary of contents
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ARM966E-S™ 16/32-Bit Flash MCU with Ethernet, USB, CAN, ■ 16/32-bit 96 MHz ARM9E based MCU – ARM966E-S RISC core: Harvard archi- tecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash) – STR91xF implementation of core adds high- speed burst Flash memory ...
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Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STR91xF 2.11 Flexible power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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A/D converter (ADC ...
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STR91xF 6.13.3 CAN interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.13.4 I2C electrical characteristics ...
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Introduction 1 Introduction STR91xF is a series of ARM-powered microcontrollers which combines a 16/32-bit ARM966E- S RISC processor core, dual-bank Flash memory, large SRAM for data or code, and a rich peripheral set to form an ideal embedded controller for ...
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STR91xF 2 Functional overview 2.1 System-in-a-Package (SiP) The STR91xF is a SiP device, comprised of two stacked die. One die is the ARM966E-S CPU with peripheral interfaces and analog functions, and the other die is the burst Flash. The two ...
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Functional overview length instructions. The PFQ will fetch 32-bits at a time from the Burst Flash memory at a rate MHz. 2.4.2 Branch Cache (BC) When instruction addresses are not sequential, such as a program branch ...
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STR91xF Figure 1. STR91xF block diagram 1.8V GND 3.0 or 3.3V GND VBATT 4 MHz to 25 MHz XTAL EMI Ctrl USB Bus To Ethernet PHY (MII USB not available on STR910 ** Ethernet MAC not available on ...
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Functional overview 2.5 SRAM (64K or 96K Bytes) A 32-bit wide SRAM resides on the CPU’s Data TCM (D-TCM) interface, providing single-cycle data accesses. As shown in High-performance Bus (AHB). Sharing is controlled by simple arbitration logic to allow the ...
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STR91xF 2.7.1 Primary Flash memory Using the STR91xF device configuration software tool possible to specify that the primary Flash memory is the default memory from which the CPU boots at reset, or otherwise specify that the secondary Flash ...
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Functional overview source, minimizing ISR latency. Typically only one interrupt source is assigned to FIQ. An FIQ interrupt has its own set of banked registers to minimize the time to make a context switch. Any of the 32 interrupt request ...
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STR91xF See Table 1 for recommended interrupt source assignments to physical IRQ interrupt channels. Interrupt source assignments are made by CPU firmware during initialization, thus establishing interrupt priorities. Table 1. Recommended IRQ Channel assignments (set by CPU firmware) VIC IRQ ...
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Functional overview 2.10 Clock control unit (CCU) The CCU generates a master clock of frequency f generates individually scaled and gated clock sources to each of the following functional blocks within the STR91xF. ● CPU, f CPUCLK ● Advanced High-performance ...
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STR91xF Figure 2. Clock control 25MHz MII_PHYCLK X1_CPU 4-25MHz X1_CPU X1_RTC X2_RTC EXTCLK_TOT1 EXTCLK_T2T3 48MHz USB_CLK48M 2.10.2 Reference clock (RCLK) The main clock (f MSTR for the ARM core and all the peripherals. The RCLK provides the divided clock for ...
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Functional overview 2.10.7 External memory interface bus clock (BCLK) The BCLK is an internal clock that controls the EMI bus. All EMI bus signals are synchronized to the BCLK. The BCLK is derived from the HCLK and the frequency can ...
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STR91xF The STR91xF supports the following three global power control modes: ● Run Mode: All clocks are on with option to gate individual clocks off via clock mask registers. ● Idle Mode: CPU and FMI clocks are off until an ...
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Functional overview 2.12.1 Independent A/D converter supply and reference voltage The ADC unit on 128-pin packages has an isolated analog voltage supply input at pin AVDD to accept a very clean voltage source, independent of the digital voltage supplies. The ...
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STR91xF 2.13 System supervisor The STR91xF monitors several system and environmental inputs and will generate a global reset, a system reset interrupt based on the nature of the input and configurable settings. A global reset clears all functions ...
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Functional overview peripheral clock from the APB, and an 8-bit clock pre-scaler is available. When enabled by firmware as a watchdog, this timer will cause a system reset if firmware fails to periodically reload this timer before the terminal count ...
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STR91xF drawn by the RTC unit on the VBATT pin is very low in this standby mode, I assumes SRAM battery backup is not enabled). 2.15 JTAG interface An IEEE-1149.1 JTAG interface on the STR91xF provides In-System-Programming (ISP) of all ...
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Functional overview Figure 3. JTAG chaining inside the STR91xF JTDO JTRSTn JTCK JTMS JTDI JRTCK 2.15.1 In-system-programming The JTAG interface is used to program or erase all memory areas of the STR91xF device. The pin RESET_INn must be asserted during ...
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STR91xF Debugging requires that an external host computer, running debug software, is connected to the STR91xF target system via hardware which converts the stream of debug data and commands from the host system’s protocol (USB, Ethernet, etc.) to the JTAG ...
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Functional overview the host computer must have a static image of the code being executed for decompressing the ETM9 data. Because of this, self-modified code cannot be traced. 2.17 Ethernet MAC interface with DMA STR91xF devices in the 128-pin package ...
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STR91xF ● Supports USB low and full-speed transfers (12 Mbps), certified to comply with the USB 2.0 specification ● Supports isochronous, bulk, control, and interrupt endpoints ● Configurable number of endpoints allowing a mixture single-buffered monodirectional ...
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Functional overview SRAM, handling of transmission requests, and interrupt generation. The CPU has access to the Message SRAM via the Message Handler using a set of 38 control registers. The follow features are supported by the CAN interface: ● Bitrates ...
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STR91xF 2 2. interfaces with DMA The STR91xF supports two independent I2C serial interfaces, designated I2C0, and I2C1. Each interface allows direct connection to an I2C bus as either a bus master or bus slave device (firmware configurable). ...
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Functional overview high-impedance state when not selected. The STR91xF supports SPI multi-Master operation because it provides collision detection. Each SSP interface on the STR91xF has the following features: ● Full-duplex, three or four-wire synchronous transfers ● Master or Slave operation ...
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STR91xF 2.24 A/D converter (ADC) The STR91xF provides an eight-channel, 10-bit successive approximation analog-to-digital converter. The ADC input pins are multiplexed with other functions on Port 4 as shown in Table 2. Following are the major ADC features: ● Fast ...
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Functional overview 2.26 Three-phase induction motor controller (IMC) The STR91xF provides an integrated controller for variable speed motor control applications. Six PWM outputs are generated on high current drive pins P6.0 to P6.5 for controlling a three- phase AC induction ...
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STR91xF only require 8 bits of address on an 8-bit multiplexed address/data bus, and have simple read, write, and latch inputs as shown in To use all 24 address bits, the following applies: 8 bits of lowest-order data and 8 ...
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Functional overview Figure 5. EMI 8-bit multiplexed connection example Figure 6. EMI 8-bit non-multiplexed connection example STR91xx EMI_BWR_WRLn 32/72 ST R91xx EMI_CS3n EMI_CS2n EMI_CS1n EMI_CS0n EMI_BWR_WRLn EMI_RDn EMI_ALE P8.7 EMI_AD7 P8.6 EMI_AD6 P8.5 EMI_AD5 P8.4 EMI_AD4 P8.3 EMI_AD3 P8.2 EMI_AD2 ...
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STR91xF 3 Related documentation Available from www.arm.com: ARM966E-S Rev 2 Technical Reference Manual Available from www.st.com: STR91xF Reference Manual STR9 Flash Programming Manual (PM0020) The above is a selected list only, a full list STR91xF application notes can be viewed ...
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Pin description 4 Pin description Figure 7. STR91xFM 80-pin package pinout P4.3 P4.2 P4.1 P4.0 VSS_VSSQ VDDQ P2.0 P2.1 P5.0 VSS VDD P5.1 P6.2 P6.3 VDDQ VSSQ P5.2 P5.3 P6.0 P6.1 1)NU (Not Used) on STR910FM devices. Pin 59 is ...
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STR91xF Figure 8. STR91xFW 128-pin package pinout P4.2 P4.1 P4.0 AVSS P7.0 P7.1 P7.2 VSSQ VDDQ P2.0 P2.1 P5.0 P7.3 P7.4 P7.5 VSS VDD P5.1 P6.2 P6.3 EMI_BWR_WRLn EMI_WRHn VDDQ VSSQ (3) PHYCLK_P5.2 P8.0 P5.3 P8.1 P6.0 P8.2 P6.1 P8.3 ...
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Pin description 4.1 Default pin functions During and just after reset, all pins on ports 0-9 default to high-impedance input mode until CPU firmware assigns other functions to the pins. This initial input mode routes all pins on ports 0-9 ...
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STR91xF Pkg Default Pin Pin Name Function GPIO_0. P0.5 I/O GP Input, HiZ GPIO_0. P0.6 I/O GP Input, HiZ GPIO_0. P0.7 I/O GP Input, HiZ GPIO_1. P1.0 I/O GP Input, HiZ GPIO_1.1, ...
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Pin description Pkg Default Pin Pin Name Function GPIO_3. P3.2 I/O GP Input, HiZ GPIO_3. P3.3 I/O GP Input, HiZ GPIO_3. P3.4 I/O GP Input, HiZ GPIO_3. P3.5 I/O GP Input, HiZ ...
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STR91xF Pkg Default Pin Pin Name Function GPIO_6. P6.0 I/O GP Input, HiZ GPIO_6. P6.1 I/O GP Input, HiZ GPIO_6. P6.2 I/O GP Input, HiZ GPIO_6. P6.3 I/O GP Input, HiZ GPIO_6.4, ...
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Pin description Pkg Default Pin Pin Name Function GPIO_8. P8.5 I/O GP Input, HiZ GPIO_8. P8.6 I/O GP Input, HiZ GPIO_8. P8.7 I/O GP Input, HiZ GPIO_9. P9.0 I/O GP Input, HiZ ...
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STR91xF Pkg Default Pin Pin Name Function Global or RESET 62 100 O System reset _OUTn output CPU oscillator 65 104 X1_CPU I or crystal input CPU crystal 64 103 X2_CPU O connection RTC oscillator 27 42 X1_RTC I or ...
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Pin description Pkg Default Pin Pin Name Function 6 9 VDDQ VDDQ VDDQ V V Source for 46 73 VDDQ V I/O and USB VDDQ V 2. VDDQ ...
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STR91xF 5 Memory mapping The ARM966E-S CPU addresses a single linear address space of 4 giga-bytes (2 address 0x0000.0000 to 0xFFFF.FFFF as shown in address 0x0000.0000, which is chip-select zero at address zero in the Flash Memory Interface (FMI). The ...
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Memory mapping When other AHB bus masters (such as a DMA controller) write to SRAM, their access is never buffered. Only the CPU can make use of buffered AHB writes. 5.4 Two independent Flash memories The STR91xF has two independent ...
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STR91xF Notes for Figure 9: STR91xx memory map on page Notes: 1 Either of the two Flash memories may be placed at CPU boot address 0x0000.0000. By default, the primary Flash memory is in boot position starting at CPU address ...
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Memory mapping Figure 9. STR91xx memory map TOTAL 4 GB CPU MEMORY SPACE 0xFFFF.FFFF VIC0 0xFFFF.F000 RESERVED 0xFC01.0000 VIC1 0xFC00.0000 RESERVED 0x8000.0000 ENET 0x7C00.0000 8-CH DMA 0x7800.0000 EMI 0x7400.0000 USB 0x7000.0000 ENET 0x6C00.0000 8-CH DMA 0x6800.0000 EMI 0x6400.0000 USB 0x6000.0000 ...
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STR91xF 6 Electrical characteristics 6.1 Absolute maximum ratings This product contains devices to protect the inputs against damage due to high static voltages. However advisable to take normal precautions to avoid application of any voltage higher than the ...
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Electrical characteristics 6.2 Operating conditions Table 4. Operating conditions Symbol V Digital CPU supply voltage DD V Digital I/O supply voltage DDQ SRAM backup and RTC supply V BATT voltage Analog ADC supply voltage AV DD (128-pin package) Analog ADC ...
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STR91xF 6.4 DC electrical characteristics V = 2.7 - 3.6V, V DDQ Table 6. DC Electrical Characteristics Symbol Parameter V Input High Level IH V Input Low Level IL Input Hysteresis V HYS Schmitt Trigger Output High Level High current ...
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Electrical characteristics 6.5 AC electrical characteristics V = 2.7 - 3.6V, V DDQ Table 7. AC electrical characteristics Symbol I Run Mode Current DDRUN I Idle Mode Current IDLE I Sleep Mode Current SLEEP I RTC Standby Current RTC_STBY I ...
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STR91xF Table 8. AC electrical characteristics Symbol Parameter f CCU Master Clk Output MSTR f CPU Core Frequency CPUCLK f Peripheral Clock for APB PCLK f Peripheral Clock for AHB HCLK f Clock Input OSC FMI Flash Bus clock (internal ...
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Electrical characteristics 6.7 Main oscillator electrical characteristics V = 2.7 - 3.6V, V DDQ Table 10. Main oscillator electrical characteristics Symbol Parameter t Oscillator Start-up Time STUP(OSC) 6.8 RTC oscillator electrical characteristics V = 2.7 - 3.6V, V DDQ Table ...
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STR91xF 6.9 PLL electrical characteristics V = 2.7 - 3.6V, V DDQ Table 13. PLL Electrical Characteristics Symbol Parameter f PLL Output Clock PLL f Clock Input OSC t PLL lock time LOCK ∆ PLL Jitter (peak to peak) t ...
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Electrical characteristics 6.10 Flash memory characteristics V = 2.7 - 3.6V, V DDQ Table 14. Flash memory program/erase characteristics Parameter Primary Bank (512 Kbytes) Primary Bank Bank erase (256 Kbytes) Secondary Bank (32 Kbytes) Of Primary Bank (64 Kbytes) Sector ...
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STR91xF 6.11 External memory bus timings V = 2.7 - 3.6V, V DDQ Table 16. EMI Bus Clock Period Symbol t BCLK Notes: 1 EMI Bus clock is an internal clock only and is not available on the EMI bus ...
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Electrical characteristics Figure 11. Non-mux bus (8-bit) read timings EMI_CSxn EMI_A [15:0] EMI_D[7:0] EMI_RDn Figure 12. Mux bus (16-bit) read timings EMI_CSxn EMI_A LE EMI_A [23:16] EMI_A D[15:0] EMI_RDn 56/72 A ddress tRA ddress tA A ...
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STR91xF Table 18. EMI write operation Symbol Parameter t WRn to CSn inactive WCR t Write Pulse Width WP Write Data Setup Time (non-mux mode) t WDS Write Data Setup Time (mux mode ) t Write Data Hold Time WDH ...
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Electrical characteristics Figure 14. Mux Bus (16-bit) Write Timings EMI_CSxn EMI_A LE EMI_A [23:16] EMI_A D[15:0] EMI_WRLn EMI_WRHn 58/ ddress tWDS A ddress tWA S STR91xF tWCR tWA H Data tWDH ...
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STR91xF 6.12 ADC electrical characteristics V = 2.7 - 3.6V, V DDQ Table 19. ADC Electrical Characteristics Symbol Parameter V Input Voltage Range AIN RES Resolution N Number of Input Channels CH f ADC Clock Frequency ADC Start Up Time ...
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Electrical characteristics Figure 15. ADC conversion characteristics Digital Result 1023 1022 V V – DDA SSA 1LSB = ---------------------------------------- - IDEAL 1024 1021 LSB ...
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STR91xF 6.13 Communication interface electrical characteristics 6.13.1 10/100 Ethernet MAC electrical characteristics V = 2.7 - 3.6V, V DDQ Ethernet MII Interface Timings Figure 16. MII_RX_CLK and MII_TX_CLK timing diagram MII_RX_TCLK, MII_TX_CLK Table 20. MII_RX_CLK and MII_TX_CLK timing table Symbol ...
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Electrical characteristics Table 22. Ethernet MII management timing table Symbol MDIO delay from rising 1 edge of MDC MDIO setup time to rising 2 edge of MDC MDIO hold time from rising 3 edge of MDC Ethernet MII transmit timings ...
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STR91xF Ethernet MII Receive timings Figure 20. Ethernet MII receive timing diagram MII_RX_CLK MII_RXD MII_RX_DV MII_RX_ER Figure 21. Ethernet MII receive timing table Symbol MII_RXD valid to 1 MII_RX_CLK high MII_RX_CLK high to 2 MII_RXD invalid 6.13.2 USB electrical interface ...
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Electrical characteristics 2 6.13 electrical characteristics V = 2.7 - 3.6V, V DDQ 2 Table 24 Electrical Characteristics Symbol Bus free time between a STOP t BUF and START condition Hold time START condition. t After ...
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STR91xF 6.13.5 SPI electrical characteristics V = 2.7 - 3.6V, V DDQ Table 25. SPI electrical characteristics Symbol f SCLK SPI clock frequency 1/t c(SCLK) t r(SCLK) SPI clock rise and fall times t f(SCLK setup time su(SS) ...
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Electrical characteristics Figure 23. SPI slave timing diagram with CPHA=1 NSS INPUT t su( NSS ) CPHA=1 CPOL=0 CPHA=1 CPOL=1 t a(SO) MISO OUTPUT MOSI INPUT Figure 24. SPI master timing diagram NSS INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 CPHA=1 CPOL=0 ...
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STR91xF 6.14 JTAG interface electrical characteristics Table 26. JTAG interface electrical characteristics Symbol t JTCK Low JTCKL t JTCK High JTCKH t JTCK Period JTCKP t JTDI, JTMS Setup before JTCK High JTSU t JTDI Hold after JTCK High JTHLD ...
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Package mechanical data 7 Package mechanical data Figure 25. 80-Pin Low Profile Quad Flat Package SEATING PLANE C ccc PIN 1 IDENTIFICATION Figure 26. 128-Pin Low Profile Quad Flat Package ...
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STR91xF 8 Ordering information Table 27. Ordering information Part Number STR910FM32X6 STR910FW32X6 STR911FM42X6 STR911FM44X6 STR912FW42X6 STR912FW44X6 Flash KB RAM KB Major Peripherals 256+32 64 256+32 64 CAN, EMI, 80 I/Os 256+32 96 USB, CAN, 48 I/Os 512+32 96 256+32 96 ...
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Ordering information Table 28. Ordering information scheme Example: Family ARM9 Microcontroller Family Series 1 = STR9 Series 1 Feature set 0 = CAN, UART, IrDA, I2C, SSP 1 = USB, CAN, UART, IrDA, I2C, SSP 2 = USB, CAN, UART, ...
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STR91xF 9 Revision history Date Revision 12-Apr-2006 1 Initial release Revision history Changes 71/72 ...
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. ...