STR910FM42X6T STMICROELECTRONICS [STMicroelectronics], STR910FM42X6T Datasheet
STR910FM42X6T
Related parts for STR910FM42X6T
STR910FM42X6T Summary of contents
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ARM966E-S™ 16/32-Bit Flash MCU with Ethernet, USB, CAN, ■ 16/32-bit 96 MHz ARM9E based MCU – ARM966E-S RISC core: Harvard archi- tecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash) – STR91xF implementation of core adds high- speed burst Flash memory ...
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Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STR91xF 2.10.11 Operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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General purpose I ...
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STR91xF 6.11.4 Electro-Static Discharge (ESD ...
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Introduction 1 Introduction STR91xF is a series of ARM-powered microcontrollers which combines a 16/32-bit ARM966E-S RISC processor core, dual-bank Flash memory, large SRAM for data or code, and a rich peripheral set to form an ideal embedded controller for a ...
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STR91xF 2 Functional overview 2.1 System-in-a-Package (SiP) The STR91xF is a SiP device, comprised of two stacked die. One die is the ARM966E-S CPU with peripheral interfaces and analog functions, and the other die is the burst Flash. The two ...
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Functional overview 2.4.2 Branch Cache (BC) When instruction addresses are not sequential, such as a program branch situation, the PFQ would have to flush and reload which would cause the CPU to stall were present. Before reloading, ...
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STR91xF Figure 1. STR91xF block diagram 1.8V GND 3.0 or 3.3V GND VBATT 4 MHz to 25 MHz XTAL EMI Ctrl USB Bus To Ethernet PHY (MII USB not available on STR910 ** Ethernet MAC not available on ...
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Functional overview 2.5 SRAM (64K or 96K Bytes) A 32-bit wide SRAM resides on the CPU’s Data TCM (D-TCM) interface, providing single-cycle data accesses. As shown in High-performance Bus (AHB). Sharing is controlled by simple arbitration logic to allow the ...
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STR91xF Flash memories are programmed half-word (16 bits time, but are erased by sector or by full array. 2.7.1 Primary Flash memory Using the STR91xF device configuration software tool and 3rd party Integrated Developer Environments possible ...
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Functional overview interrupt output signals to the CPU. The output signals are FIQ and IRQ, with FIQ having higher priority. 2.9.1 FIQ handling FIQ (Fast Interrupt reQuest) is the only non-vectored interrupt and the CPU can execute an Interrupt Service ...
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STR91xF See Table 2 for recommended interrupt source assignments to physical IRQ interrupt channels. Interrupt source assignments are made by CPU firmware during initialization, thus establishing interrupt priorities. Table 2. Recommended IRQ Channel assignments (set by CPU firmware) VIC IRQ ...
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Functional overview 2.10 Clock control unit (CCU) The CCU generates a master clock of frequency f generates individually scaled and gated clock sources to each of the following functional blocks within the STR91xF. ● CPU, f CPUCLK ● Advanced High-performance ...
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STR91xF Figure 2. Clock control 4.096 kHz JRTCLK 25MHz MII_PHYCLK X1_CPU 4-25MHz X1_CPU X1_RTC X2_RTC EXTCLK_T0T1 EXTCLK_T2T3 48MHz USB_CLK48M 2.10.2 Reference clock (RCLK) The main clock (f MSTR for the ARM core and all the peripherals. The RCLK provides the ...
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Functional overview 2.10.6 Baud rate clock (BRCLK) The baud rate clock is an internal clock derived from f UART peripherals for baudrate generation. The frequency can be optionally divided by 2. 2.10.7 External memory interface bus clock (BCLK) The BCLK ...
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STR91xF 2.11 Flexible power management The STR91xF offers configurable and flexible power management control that allows the user to choose the best power option to fit the application. Power consumption can be dynamically managed by firmware and hardware to match ...
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Functional overview ● Some resets (external reset pin, low-voltage, power-up, JTAG debug command) ● RTC alarm ● Input from wake-up unit 2.12 Voltage supplies The STR91xF requires two separate operating voltage supplies. The CPU and memories operate from a 1.65V ...
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STR91xF 2.13 System supervisor The STR91xF monitors several system and environmental inputs and will generate a global reset, a system reset interrupt based on the nature of the input and configurable settings. A global reset clears all functions ...
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Functional overview peripheral clock from the APB, and an 8-bit clock pre-scaler is available. When enabled by firmware as a watchdog, this timer will cause a system reset if firmware fails to periodically reload this timer before the terminal count ...
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STR91xF an alternate power source, such as a battery, is connected to the VBATT input pin. The current drawn by the RTC unit on the VBATT pin is very low in this standby mode, I 2.15 JTAG interface An IEEE-1149.1 ...
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Functional overview Figure 3. JTAG chaining inside the STR91xF JTDO JTRSTn JTCK JTMS JTDI JRTCK 2.15.1 In-system-programming The JTAG interface is used to program or erase all memory areas of the STR91xF device. The pin RESET_INn must be asserted during ...
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STR91xF Debugging requires that an external host computer, running debug software, is connected to the STR91xF target system via hardware which converts the stream of debug data and commands from the host system’s protocol (USB, Ethernet, etc.) to the JTAG ...
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Functional overview the host computer must have a static image of the code being executed for decompressing the ETM9 data. Because of this, self-modified code cannot be traced. 2.17 Ethernet MAC interface with DMA STR91xF devices in 128-pin packages provide ...
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STR91xF ● Supports USB low and full-speed transfers (12 Mbps), certified to comply with the USB 2.0 specification ● Supports isochronous, bulk, control, and interrupt endpoints ● Configurable number of endpoints allowing a mixture single-buffered monodirectional ...
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Functional overview SRAM, handling of transmission requests, and interrupt generation. The CPU has access to the Message SRAM via the Message Handler using a set of 38 control registers. The follow features are supported by the CAN interface: ● Bitrates ...
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STR91xF 2 2. interfaces with DMA The STR91xF supports two independent I2C serial interfaces, designated I2C0, and I2C1. Each interface allows direct connection to an I2C bus as either a bus master or bus slave device (firmware configurable). ...
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Functional overview high-impedance state when not selected. The STR91xF supports SPI multi-Master operation because it provides collision detection. Each SSP interface on the STR91xF has the following features: ● Full-duplex, three or four-wire synchronous transfers ● Master or Slave operation ...
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STR91xF 2.24 A/D converter (ADC) The STR91xF provides an eight-channel, 10-bit successive approximation analog-to-digital converter. The ADC input pins are multiplexed with other functions on Port 4 as shown in Table 3. Following are the major ADC features: ● Fast ...
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Functional overview 2.25.1 DMA A programmable DMA channel may be assigned by CPU firmware to service each timer/ counter module TIM0 and TIM1 for fast and direct transfers. 2.26 Three-phase induction motor controller (IMC) The STR91xF provides an integrated controller ...
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STR91xF respectively. The output signal EMI_RDn is the read strobe for both the low and high data bytes. ● 8-bit multiplexed data mode: This is a variant of the 16-bit multiplexed mode. Although this mode can provide 24 bits of ...
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Functional overview Figure 5. EMI 8-bit multiplexed connection example Figure 6. EMI 8-bit non-multiplexed connection example STR91xx EMI_BWR_WRLn 32/73 ST R91xx EMI_CS3n EMI_CS2n EMI_CS1n EMI_CS0n EMI_BWR_WRLn EMI_RDn EMI_ALE P8.7 EMI_AD7 P8.6 EMI_AD6 P8.5 EMI_AD5 P8.4 EMI_AD4 P8.3 EMI_AD3 P8.2 EMI_AD2 ...
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STR91xF 3 Related documentation Available from www.arm.com: ARM966E-S Rev 2 Technical Reference Manual Available from www.st.com: STR91xF Reference Manual STR9 Flash Programming Manual (PM0020) The above is a selected list only, a full list STR91xF application notes can be viewed ...
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Pin description 4 Pin description Figure 7. STR91xFM 80-pin package pinout P4.3 P4.2 P4.1 P4.0 VSS_VSSQ VDDQ P2.0 P2.1 P5.0 VSS VDD P5.1 P6.2 P6.3 VDDQ VSSQ P5.2 P5.3 P6.0 P6 (Not Used) on STR910FM devices. Pin 59 ...
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STR91xF Figure 8. STR91xFW 128-pin package pinout P4.2 P4.1 P4.0 AVSS P7.0 P7.1 P7.2 VSSQ VDDQ P2.0 P2.1 P5.0 P7.3 P7.4 P7.5 VSS VDD P5.1 P6.2 P6.3 EMI_BWR_WRLn EMI_WRHn VDDQ VSSQ (3) PHYCLK_P5.2 P8.0 P5.3 P8.1 P6.0 P8.2 P6.1 P8.3 ...
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Pin description 4.1 Default pin functions During and just after reset, all pins on ports 0-9 default to high-impedance input mode until CPU firmware assigns other functions to the pins. This initial input mode routes all pins on ports 0-9 ...
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STR91xF Pkg Default Pin Pin Name Function GPIO_0. P0.6 I/O GP Input, HiZ GPIO_0. P0.7 I/O GP Input, HiZ GPIO_1. P1.0 I/O GP Input, HiZ GPIO_1. P1.1 I/O GP Input, HiZ GPIO_1.2, ...
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Pin description Pkg Default Pin Pin Name Function GPIO_3. P3.7 I/O GP Input, HiZ GPIO_4. P4.0 I/O GP Input, HiZ GPIO_4. P4.1 I/O GP Input, HiZ GPIO_4. P4.2 I/O GP Input, HiZ ...
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STR91xF Pkg Default Pin Pin Name Function GPIO_7. P7.0 I/O GP Input, HiZ GPIO_7. P7.1 I/O GP Input, HiZ GPIO_7. P7.2 I/O GP Input, HiZ GPIO_7. P7.3 I/O GP Input, HiZ GPIO_7.4, ...
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Pin description Pkg Default Pin Pin Name Function EMI_BWR EMI byte write _WRLn strobe (8 bit - 21 O mode) or low (used as byte write strobe EMI_LBn in (16 bit mode) future rev.) EMI_WRHn EMI high byte (used as ...
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STR91xF Pkg Default Pin Pin Name Function ADC reference - 123 AVREF V voltage input Combined ADC ref voltage and AVREF ADC analog _AVDD voltage source, 2.7V - 3.6V Standby voltage input for RTC 24 39 VBATT ...
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Memory mapping 5 Memory mapping The ARM966E-S CPU addresses a single linear address space of 4 giga-bytes (2 address 0x0000.0000 to 0xFFFF.FFFF as shown in address 0x0000.0000, which is chip-select zero at address zero in the Flash Memory Interface (FMI). ...
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STR91xF When other AHB bus masters (such as a DMA controller) write to SRAM, their access is never buffered. Only the CPU can make use of buffered AHB writes. 5.4 Two independent Flash memories The STR91xF has two independent Flash ...
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Memory mapping Notes for Figure 9: STR91xF memory map on page Notes: 1 Either of the two Flash memories may be placed at CPU boot address 0x0000.0000. By default, the primary Flash memory is in boot position starting at CPU ...
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STR91xF Figure 9. STR91xF memory map TOTAL 4 GB CPU MEMORY SPACE 0xFFFF.FFFF VIC0 0xFFFF.F000 RESERVED 0xFC01.0000 VIC1 0xFC00.0000 RESERVED 0x8000.0000 ENET 0x7C00.0000 8-CH DMA 0x7800.0000 EMI 0x7400.0000 USB 0x7000.0000 ENET 0x6C00.0000 8-CH DMA 0x6800.0000 EMI 0x6400.0000 USB 0x6000.0000 APB1 ...
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Electrical characteristics 6 Electrical characteristics 6.1 Absolute maximum ratings This product contains devices to protect the inputs against damage due to high static voltages. However advisable to take normal precautions to avoid application of any voltage higher than ...
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STR91xF 6.2 Operating conditions Table 5. Operating conditions Symbol V Digital CPU supply voltage DD V Digital I/O supply voltage DDQ SRAM backup and RTC supply (1) V BATT voltage Analog ADC supply voltage AV DD (128-pin package) Analog ADC ...
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Electrical characteristics 6.4 DC electrical characteristics V = 2.7 - 3.6V, V DDQ Table 7. DC Electrical Characteristics Symbol Parameter V Input High Level IH V Input Low Level IL Input Hysteresis V HYS Schmitt Trigger Output High Level High ...
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STR91xF 6.5 AC electrical characteristics V = 2.7 - 3.6V, V DDQ Table 8. AC electrical characteristics Symbol Parameter I Run Mode Current DDRUN I Idle Mode Current IDLE I Sleep Mode Current SLEEP I RTC Standby Current RTC_STBY I ...
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Electrical characteristics Table 9. AC electrical characteristics Symbol Parameter f CCU Master Clk Output MSTR f CPU Core Frequency CPUCLK f Peripheral Clock for APB PCLK f Peripheral Clock for AHB HCLK f Clock Input OSC FMI Flash Bus clock ...
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STR91xF 6.7 Main oscillator electrical characteristics V = 2.7 - 3.6V, V DDQ Table 11. Main oscillator electrical characteristics Symbol Parameter t Oscillator Start-up Time STUP(OSC) 6.8 RTC oscillator electrical characteristics V = 2.7 - 3.6V, V DDQ Table 12. ...
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Electrical characteristics 6.9 PLL electrical characteristics V = 2.7 - 3.6V, V DDQ Table 14. PLL Electrical Characteristics Symbol Parameter f PLL Output Clock PLL f Clock Input OSC t PLL lock time LOCK ∆ PLL Jitter (peak to peak) ...
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STR91xF 6.10 Flash memory characteristics V = 2.7 - 3.6V, V DDQ Table 15. Flash memory program/erase characteristics Parameter Primary Bank (512 Kbytes) Primary Bank Bank erase (256 Kbytes) Secondary Bank (32 Kbytes) Of Primary Bank (64 Kbytes) Sector erase ...
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Electrical characteristics 6.11 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. 6.11.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is ...
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STR91xF 6.11.3 Absolute Maximum Ratings (Electrical Sensitivity) Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to ...
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Electrical characteristics ● Critical Data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 ...
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STR91xF Symbol Parameter t Address to ALE hold time AAH t Address to ALE setup time (ALE_LENGTH AAS Notes: 1 ALE_LENGTH = 1 by default (can be programmed setting the bits In the SCU_SCR0 ...
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Electrical characteristics Table 22. EMI write operation Symbol Parameter t WRn to CSn inactive WCR t Write Pulse Width WP Write Data Setup Time (non-mux mode) t WDS Write Data Setup Time (mux mode ) Write Data Hold t WDH ...
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STR91xF Figure 13. Non-Mux Bus (8-bit) write timings EMI_CSxn EMI_A[15:0] EMI_D[7:0] EMI_BWR_WRLn Figure 14. Mux Bus (16-bit) Write Timings EMI_CSxn EMI_A LE EMI_A [23:16] EMI_A D[15:0] EMI_WRLn EMI_WRHn Address Data tWAS tWDS ddress ...
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Electrical characteristics 6.13 ADC electrical characteristics V = 2.7 - 3.6V, V DDQ Table 23. ADC Electrical Characteristics Symbol Parameter V Input Voltage Range AIN RES Resolution N Number of Input Channels CH f ADC Clock Frequency ADC POR bit ...
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STR91xF Figure 15. ADC conversion characteristics Digital Result 1023 1022 V V – DDA SSA 1LSB = ---------------------------------------- - IDEAL 1021 1024 LSB ...
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Electrical characteristics 6.14 Communication interface electrical characteristics 6.14.1 10/100 Ethernet MAC electrical characteristics V = 2.7 - 3.6V, V DDQ Ethernet MII Interface Timings Figure 16. MII_RX_CLK and MII_TX_CLK timing diagram MII_RX_TCLK, MII_TX_CLK Table 24. MII_RX_CLK and MII_TX_CLK timing table ...
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STR91xF Table 26. Ethernet MII management timing table Symbol MDIO delay from rising 1 edge of MDC MDIO setup time to rising 2 edge of MDC MDIO hold time from rising 3 edge of MDC Ethernet MII transmit timings Figure ...
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Electrical characteristics Ethernet MII Receive timings Figure 20. Ethernet MII receive timing diagram MII_RX_CLK MII_RXD MII_RX_DV MII_RX_ER Figure 21. Ethernet MII receive timing table Symbol MII_RXD valid to 1 MII_RX_CLK high MII_RX_CLK high to 2 MII_RXD invalid 6.14.2 USB electrical ...
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STR91xF 2 6.14 electrical characteristics V = 2.7 - 3.6V, V DDQ 2 Table 28 Electrical Characteristics Symbol Bus free time between a STOP t BUF and START condition Hold time START condition. t After this ...
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Electrical characteristics 6.14.5 SPI electrical characteristics V = 2.7 - 3.6V, V DDQ Table 29. SPI electrical characteristics Symbol f SCLK SPI clock frequency 1/t c(SCLK) t r(SCLK) SPI clock rise and fall times t f(SCLK setup time ...
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STR91xF Figure 23. SPI slave timing diagram with CPHA=1 NSS INPUT t su( NSS ) CPHA=1 CPOL=0 CPHA=1 CPOL=1 t a(SO) MISO OUTPUT MOSI INPUT Figure 24. SPI master timing diagram NSS INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 ...
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Package mechanical data 7 Package mechanical data Figure 25. 80-Pin Low Profile Quad Flat Package SEATING PLANE C ccc PIN 1 IDENTIFICATION 128-Pin Low Profile Quad Flat Package SEATING PLANE ...
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STR91xF 7.1 Thermal characteristics The average chip-junction temperature, T The average chip-junction temperature, T following equation: x Θ Where: is the Ambient Temperature in °C, – Θ is the Package ...
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Ordering information 8 Ordering information Table 31. Ordering information Part Number STR910FM32X6 STR910FW32X6 STR911FM42X6 STR911FM44X6 STR912FW42X6 STR912FW44X6 70/73 Flash KB RAM KB Major Peripherals 256+32 64 256+32 64 CAN, EMI, 80 I/Os 256+32 96 USB, CAN, 40 I/Os 512+32 96 ...
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STR91xF Table 32. Ordering information scheme Example: Family ARM9 Microcontroller Family Series 1 = STR9 Series 1 Feature set 0 = CAN, UART, IrDA, I2C, SSP 1 = USB, CAN, UART, IrDA, I2C, SSP 2 = USB, CAN, UART, IrDA, ...
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Revision history 9 Revision history Date Revision 12-Apr-2006 28-June-2006 04-Sep-2006 01-Feb-2007 72/73 1 Initial release Added LFBGA144 package 2 Updated electrical characteristics section Changed number of GPIOs in 80 pin packge to 40 Changed EMI_RDYn pin name to EMI_WAITn 3 ...
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STR91xF Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at ...