UPSD3254 STMICROELECTRONICS [STMicroelectronics], UPSD3254 Datasheet - Page 116

• Manufacturer Part Number: UPSD3254
• Description: Flash Programmable System Devices with 8032 Microcontroller Core
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
Example. FS0 is valid when the address is in the
range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to
87FFh. Any address in the range of RS0 always
accesses the SRAM. Any address in the range of
CSBOOT0 greater than 87FFh (and less than
9FFFh) automatically addresses secondary Flash
memory segment 0. Any address greater than
9FFFh accesses the primary Flash memory seg-
ment 0. You can see that half of the primary Flash
memory segment 0 and one-fourth of secondary
Flash memory segment 0 cannot be accessed in
this example.
Note: An equation that defined FS1 to anywhere
in the range of 8000h to BFFFh would not be valid.
Figure 54 shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must
not overlap. Level one has the highest priority and
level 3 has the lowest.
Memory Select Configuration in Program and
Data Spaces. The MCU Core has separate ad-
dress spaces for Program memory and Data
memory. Any of the memories within the PSD
MODULE can reside in either space or both spac-
es. This is controlled through manipulation of the
VM Register that resides in the CSIOP space.
The VM Register is set using PSDsoft Express to
have an initial value. It can subsequently be
Table 88. VM Register
116/175
0 = disable
PIO Mode
1= enable
PIO Mode
PIO_EN
Bit 7
not used
not used
Bit 6
not used
not used
Bit 5
0 = RD
can’t
access
Flash
memory
1 = RD
access
Flash
memory
FL_Data
Primary
Bit 4
0 = RD can’t
access Secondary
Flash memory
1 = RD access
Secondary Flash
memory
Secondary Data
Bit 3
changed by the MCU so that memory mapping
can be changed on-the-fly.
For example, you may wish to have SRAM and pri-
mary Flash memory in the Data space at Boot-up,
and secondary Flash memory in the Program
space at Boot-up, and later swap the primary and
secondary Flash memories. This is easily done
with the VM Register by using PSDsoft Express
Configuration to configure it for Boot-up and hav-
ing the MCU change it when desired. Table 88 de-
scribes the VM Register.
Figure 54. Priority Level of Memory and I/O
Components in the PSD MODULE
Highest Priority
Lowest Priority
0 = PSEN
can’t
access
Flash
memory
1 = PSEN
access
Flash
memory
FL_Code
Primary
Bit 2
Primary Flash Memory
Non-Volatile Memory
0 = PSEN can’t
access Secondary
Flash memory
1 = PSEN access
Secondary Flash
memory
Secondary Code
SRAM, I /O, or
Peripheral I /O
Secondary
Level 1
Level 2
Level 3
Bit 1
0 = PSEN
can’t
access
SRAM
1 = PSEN
access
SRAM
SRAM_Code
Bit 0
AI02867D