ISPPAC-CLK5510V LATTICE [Lattice Semiconductor], ISPPAC-CLK5510V Datasheet - Page 11

• Manufacturer Part Number: ISPPAC-CLK5510V
• Description: In-System Programmable Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Timing Specifications
Skew Matching
Programmable Skew Control
Control Functions
Figure 6. RESET and Profile Select Timing
t
SK
t
t
1. Skew control range is a function of VCO frequency (f
2. Skew step size is a function of VCO frequency (f
3. Only applicable to outputs with non-zero skew settings.
t
t
t
t
t
1. Output clock cycles for the particular output being controlled.
t
SKRANGE
SKSTEP
SKERR
DIS/OE
DIS/GOE
SUSGATE
PLL_RSTW
HPS_RST
SKEW
Symbol
In coarse skew mode T
In coarse skew mode T
STEPS
Symbol
Symbol
Output-output Skew
Delay Time, OEX or OEY to Output Disabled/
Enabled
Delay Time, GOE to Output Disabled/Enabled
Setup Time, SGATE to Output Clock Start/
Stop
PLL Reset Pulse Width
Hold time for RESET past change in PS[0..1]
Skew Control Range
Skew Steps per range
Skew Step Size
Skew Time Accuracy
Parameter
PS[0..1]
RESET
SKRANGE
SKSTEP
Parameter
= 1/(4 x f
= 15/(4 x f
2
Parameter
Between any two identically configured and loaded
outputs regardless of bank and output frequency
1
3
VCO
VCO
).
Fine Skew Mode, f
Fine Skew Mode, f
Coarse Skew Mode, f
Coarse Skew Mode, f
Fine Skew Mode, f
Fine Skew Mode, f
Coarse Skew Mode, f
Coarse Skew Mode, f
Fine skew mode
Coarse skew mode
).
VCO
). In fine skew mode T
VCO
). In fine skew mode T
Conditions
Conditions
t
PLL_RSTW
VCO
VCO
VCO
VCO
11
VCO
VCO
VCO
VCO
= 320 MHz
= 640 MHz
= 320 MHz
= 640 MHz
= 320 MHz
= 640 MHz
= 320 MHz
= 640 MHz
SKSTEP
Conditions
t
HPS_RST
SKRANGE
= 1/(8 x f
ispClock5500 Family Data Sheet
= 15/(8 x f
VCO
Min.
—
—
—
—
—
—
—
—
—
—
—
).
VCO
Min.
Min.
—
15
20
—
—
).
3
11.72
Typ.
5.86
2.93
5.86
390
195
780
390
16
30
50
Typ.
Typ.
10
10
—
—
—
—
Max.
—
—
—
—
—
—
—
—
—
—
—
Max.
Max.
50
20
20
—
—
—
Units
cycles
Units
Units
ns
ps
ps
ps
ns
ns
µs
ns
1