M24M01 STMicroelectronics, M24M01 Datasheet
M24M01
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M24M01 Summary of contents
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... FEATURES SUMMARY 400 kHz High Speed Two Wire I Interface Single Supply Voltage: – 2.7V to 3.6V for M24M01-V – 1.8V to 3.6V for M24M01-S Write Control Input BYTE and PAGE WRITE (up to 128 Bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Behavior ...
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... M24M01 SUMMARY DESCRIPTION The M24M01 Mbit (131,072 x 8) electrically erasable programmable memory (EEPROM) ac- 2 cessed C-compatible bus. Figure 2. Logic Diagram E1-E2 M24M01 SCL Table 1. Signal Names E1, E2 Chip Enable SDA Serial Data SCL Serial Clock WC Write Control V Supply Voltage ...
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... Select and Address bytes are acknowledged, . (Fig- CC Data bytes are not acknowledged. BUS fc = 100kHz fc = 400kHz 100 C BUS (pF establish the Device Select Code. (see Tables 10 and IL , and Write operations are al for Bus SDA MASTER SCL C BUS 1000 M24M01 C BUS AI01665 3/19 ...
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... A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24M01 device is always a slave in all communication. Start Condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state ...
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... 128 IL STOP Condition ACK ACK STOP Condition Initial Sequence START, Device Select START, Device Select Address reSTART, Device Select Similar to Current or Random Address Read START, Device Select START, Device Select M24M01 AI00792B 5/19 ...
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... M24M01 Figure 6. Write Mode Sequences with WC=1 (data write inhibited) WC BYTE WRITE DEV SEL WC PAGE WRITE DEV SEL WC (cont'd) NO ACK PAGE WRITE (cont'd) Write Operations Following a Start condition the bus master sends a Device Select Code with the RW bit reset to 0. The device acknowledges this, as shown in Figure 7, and waits for two address bytes ...
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... The transfer is terminated by the bus master generat- ing a Stop condition. ACK ACK DEV SEL BYTE ADDR BYTE ADDR R/W ACK ACK DEV SEL BYTE ADDR BYTE ADDR R/W ACK ACK DATA IN N M24M01 ACK ACK DATA IN ACK ACK DATA IN 1 DATA IN 2 AI01106C 7/19 ...
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... M24M01 Figure 8. Write Cycle Polling Flowchart using ACK First byte of instruction with already decoded by the device NO ReSTART STOP Minimizing System Delays by Polling On ACK During the internal Write cycle, the device discon- nects itself from the bus, and writes a copy of the data from its internal latches to the memory cells ...
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... The counter is then incremented. The bus master terminates the ACK ACK NO ACK DEV SEL * DATA OUT R/W ACK NO ACK DATA OUT N ACK ACK ACK DEV SEL * DATA OUT 1 R/W AI01105C st th and 4 bytes) must be identical. M24M01 9/19 ...
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... M24M01 transfer with a Stop condition, as shown in Figure 9, without acknowledging the byte. Sequential Read This operation can be used after a Current Ad- dress Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the de- vice continues to output the next byte in sequence ...
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... JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter 2 , R2=500 ) M24M01 Min. Max. Unit –65 150 °C 1 °C 235 – ...
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... The parameters in the DC and AC Characteristic tables that follow are de- rived from tests performed under the Measure- Table 5. Operating Conditions (M24M01-V) Symbol V Supply Voltage CC T Ambient Operating Temperature A Table 6. Operating Conditions (M24M01-S) Symbol V Supply Voltage CC T Ambient Operating Temperature A Table 7. AC Measurement Conditions Symbol C ...
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... Table 9. Power-Up Timing and V Symbol Parameter Time delay to Read or Write instruction Threshold Voltage th Note: 1. These parameters are characterized only. Table 10. DC Characteristics (M24M01-V) Symbol Parameter Input Leakage Current I LI (SCL, SDA, E1, E2, WC) I Output Leakage Current LO I Supply Current CC I Stand-by Supply Current ...
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... M24M01 Table 12. AC Characteristics Test conditions specified in Table 7 and Table 5 or Table 6 Symbol Alt Clock Frequency C SCL t t Clock Rise Time CH1CH2 Clock Fall Time CL1CL2 Clock Pulse Width High CHCL HIGH t t Clock Pulse Width Low CLCH ...
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... Figure 11. AC Waveforms tCHCL SCL tDLCL SDA In tCHDX START Condition SCL SDA In tCHDH STOP Condition SCL tCLQV SDA Out tCLCH tCLDX tDXCX SDA Change SDA Input tW Write Cycle tCLQX Data Valid M24M01 tCHDH tDHDL STOP START Condition Condition tCHDX START Condition AI00795C 15/19 ...
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... M24M01 PACKAGE MECHANICAL LGA8 - 8 lead Land Grid Array, Package Outline E A1 Notes: 1. Drawing is not to scale. LGA8 - 8 lead Land Grid Array, Package Mechanical Data Symb. Typ. A 1.040 A1 0.340 A2 0.700 D 8.000 D1 0.100 E 5.000 E1 1.270 E2 3.810 E3 0.390 k 0.100 T1 0.410 T2 0.670 T3 0.970 ddd 0.100 16/19 CONTACT 1 ...
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... 1.8 to 3.6V CC Package LA = LGA8 (Land Grid Array) Temperature Range 6 = – °C Option T = Tape & Reel Packing For a list of available options (speed, package, etc.) or for further information on any aspect of this M24M01 – device, please contact your nearest ST Sales Of- fice. M24M01 T 17/19 ...
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... M24M01 REVISION HISTORY Table 14. Document Revision History Date Rev. LGA8 Package mechanical data updated 02-Oct-2001 1.0 Datasheet released as Product Preview Table added on Power-up Timing 21-Jun-2002 1.1 Full Datasheet released 08-Jan-2003 1.2 Added LGA maximum rating for soldering temperature 18/19 Description of Revision ...
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... India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners © 2003 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies www.st.com M24M01 19/19 ...