M28W320 STMicroelectronics, M28W320 Datasheet - Page 10

• Manufacturer Part Number: M28W320
• Description: 32 Mbit 2Mb x16/ Boot Block Low Voltage Flash Memory
• Manufacturer: STMicroelectronics

M28W320CT, M28W320CB
Table 10. Instructions
Note: 1. X = Don’t Care.
Erase (EE)
Block erasure sets all the bits within the selected
block to ’1’. One block at a time can be erased. It
is not necessary to program the block with 00h as
the P/E.C. will do it automatically before erasing.
This instruction uses two write cycles. The first
command written is the Erase Set up command
20h. The second command is the Erase Confirm
command D0h. An address within the block to be
erased is given and latched into the memory dur-
ing the input of the second command. If the sec-
ond command given is not an erase confirm, the
status register bits b4 and b5 are set and the in-
struction aborts.
Read operations output the status register after
erasure has started.
10/42
CLRS
DPG
monic
RSIG
RCFI
RSR
Mne-
PES
PER
PRP
RD
PG
EE
BP
BU
BL
2. The first cycle of the RD, RSR, RSIG or RCFI instruction is followed by read operations in the memory array or special register. Any
3. The signature address recognized are listed in the Tables 6, 7 and 8.
4. Address 1 and Address 2 must be consecutive address differing only for address bit A0.
5. A read cycle after a CLSR instruction will output the memory array.
(4)
(5)
number of read cycle can occur after one command cycle.
Read Memory
Array
Read Status
Register
Read
Electronic
Signature
Read CFI
Erase
Program
Double Word
Program
Clear Status
Register
Program/
Erase
Suspend
Program/
Erase
Resume
Block Protect
Block
Unprotect
Block Lock
Protection
Register
Program
Instruction
Cycles
1+
1+
1+
1+
2
2
3
1
1
1
2
2
2
2
Operat. Addr.
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
1st Cycle
55h
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)
90h or
98h or
40h or
Data
FFh
B0h
D0h
C0h
70h
98h
90h
20h
10h
30h
50h
60h
60h
60h
Read
Read
Read
Read
Operat.
Write
Write
Write
Write
Write
Write
Write
Status Register bit b7 returns ’0’ while the erasure
is in progress and ’1’ when it has completed. After
completion the Status Register bit b5 returns ’1’ if
there has been an Erase Failure. Status register
bit b1 returns ’1’ if the user is attempting to pro-
gram a protected block. Status Register bit b3 re-
turns a ’1’ if V
Erase aborts if RP turns to V
cannot be guaranteed when the erase operation is
aborted, the erase must be repeated. A Clear Sta-
tus Register instruction must be issued to reset b1,
b3, b4 and b5 of the Status Register. During the
execution of the erase by the P/E.C., the memory
accepts only the RSR (Read Status Register) and
PES (Program/Erase Suspend) instructions.
(2)
(2)
(2)
(2)
Address
Address 1
2nd Cycle
Signature
Address
Address
Address
Address
Address
Address
Address
Address
Addr.
Block
Block
Block
Read
Block
CFI
X
PP
(3)
is below V
Register
Status
Query
Data
Data
Data
Data
Input
Data
Input
Data
Input
D0h
D0h
01h
2Fh
Operat.
Write
PPLK
IL
. As data integrity
.
3nd Cycle
Address 2
Addr.
Data
Input
Data