ATTIny2313-16MI ATMEL Corporation, ATTIny2313-16MI Datasheet - Page 109

• Manufacturer Part Number: ATTIny2313-16MI
• Description: 8-bit AVR Microcontroller with 2K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Timer/Counter1 Control
Register C – TCCR1C
Timer/Counter1 – TCNT1H
and TCNT1L
Output Compare Register 1 A
– OCR1AH and OCR1AL
2543C–AVR–12/03
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will
clock the counter even if the pin is configured as an output. This feature allows software
control of the counting.
• Bit 7 – FOC1A: Force Output Compare for Channel A
• Bit 6 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM
mode. However, for ensuring compatibility with future devices, these bits must be set to
zero when TCCR1A is written when operating in a PWM mode. When writing a logical
one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform
Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits
setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is
the value present in the COM1x1:0 bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear
Timer on Compare match (CTC) mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give
direct access, both for read and for write operations, to the Timer/Counter unit 16-bit
counter. To ensure that both the high and low bytes are read and written simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit tempo-
rary high byte register (TEMP). This temporary register is shared by all the other 16-bit
registers. See “Accessing 16-bit Registers” on page 86.
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing
a compare match between TCNT1 and one of the OCR1x Registers.
Writing to the TCNT1 Register blocks (removes) the compare match on the following
timer clock for all compare units.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
FOC1A
R/W
R/W
W
7
0
7
0
7
0
FOC1B
R/W
R/W
W
6
0
6
0
6
0
R/W
R/W
R
5
–
0
5
0
5
0
R/W
R/W
OCR1A[15:8]
TCNT1[15:8]
R
4
0
4
0
4
–
0
OCR1A[7:0]
TCNT1[7:0]
R/W
R/W
3
0
3
0
R
3
–
0
R/W
R/W
2
0
2
0
R
2
–
0
ATtiny2313/V
R/W
R/W
1
0
1
0
R
1
–
0
R/W
R/W
0
0
0
0
R
0
–
0
OCR1AH
OCR1AL
TCNT1H
TCNT1L
TCCR1C
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