ATTIny2313-16MI ATMEL Corporation, ATTIny2313-16MI Datasheet - Page 157

• Manufacturer Part Number: ATTIny2313-16MI
• Description: 8-bit AVR Microcontroller with 2K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

EEPROM Write Prevents
Writing to SPMCSR
Reading the Fuse and Lock
Bits from Software
2543C–AVR–12/03
Note that an EEPROM write operation will block all software programming to Flash.
Reading the Fuses and Lock bits from software will also be prevented during the
EEPROM write operation. It is recommended that the user checks the status bit (EEWE)
in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR
Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits,
load the Z-pointer with 0x0001 and set the RFLB and SPMEN bits in SPMCSR. When
an LPM instruction is executed within three CPU cycles after the RFLB and SPMEN bits
are set in SPMCSR, the value of the Lock bits will be loaded in the destination register.
The RFLB and SPMEN bits will auto-clear upon completion of reading the Lock bits or if
no LPM instruction is executed within three CPU cycles or no SPM instruction is exe-
cuted within four CPU cycles. When RFLB and SPMEN are cleared, LPM will work as
described in the Instruction set Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for
reading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and
set the RFLB and SPMEN bits in SPMCSR. When an LPM instruction is executed within
three cycles after the RFLB and SPMEN bits are set in the SPMCSR, the value of the
Fuse Low byte (FLB) will be loaded in the destination register as shown below. Refer to
Table 69 on page 161 for a detailed description and mapping of the Fuse Low byte.
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM
instruction is executed within three cycles after the RFLB and SPMEN bits are set in the
SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination regis-
ter as shown below. Refer to Table XXX on page xxx for detailed description and
mapping of the Fuse High byte.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that
are unprogrammed, will be read as one.
Bit
Rd
Bit
Rd
Bit
Rd
FLB7
FHB7
7
–
7
7
FLB6
FHB6
6
6
6
–
FHB5
FLB5
5
5
5
–
FHB4
FLB4
4
–
4
4
FLB3
FHB3
3
–
3
3
FHB2
FLB2
2
–
2
2
ATtiny2313/V
FHB1
FLB1
LB2
1
1
1
FHB0
FLB0
LB1
0
0
0
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