ATTIny2313-16MI ATMEL Corporation, ATTIny2313-16MI Datasheet - Page 110

• Manufacturer Part Number: ATTIny2313-16MI
• Description: 8-bit AVR Microcontroller with 2K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Output Compare Register 1 B
- OCR1BH and OCR1BL
Input Capture Register 1 –
ICR1H and ICR1L
Timer/Counter Interrupt Mask
Register – TIMSK
110
ATtiny2313/V
The Output Compare Registers contain a 16-bit value that is continuously compared
with the counter value (TCNT1). A match can be used to generate an Output Compare
interrupt, or to generate a waveform output on the OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low
bytes are written simultaneously when the CPU writes to these registers, the access is
performed using an 8-bit temporary high byte register (TEMP). This temporary register
is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 86.
The Input Capture is updated with the counter (TCNT1) value each time an event occurs
on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1).
The Input Capture can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes
are read simultaneously when the CPU accesses these registers, the access is per-
formed using an 8-bit temporary high byte register (TEMP). This temporary register is
shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 86.
• Bit 7 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 44.) is executed when the TOV1 flag, located
in TIFR, is set.
• Bit 6 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 44.) is executed when the
OCF1A flag, located in TIFR, is set.
• Bit 5 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 44.) is executed when the
OCF1B flag, located in TIFR, is set.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
TOIE1
R/W
R/W
R/W
7
0
7
0
7
0
OCIE1A
R/W
R/W
R/W
6
0
6
0
6
0
OCIE1B
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
OCR1B[15:8]
4
0
4
0
OCR1B[7:0]
R
4
–
0
ICR1[15:8]
ICR1[7:0]
R/W
R/W
ICIE1
R/W
3
0
3
0
3
0
OCIE0B
R/W
R/W
R/W
2
0
2
0
2
0
TOIE0
R/W
R/W
R/W
1
0
1
0
1
0
OCIE0A
R/W
R/W
R/W
0
0
0
0
2543C–AVR–12/03
0
0
OCR1BH
OCR1BL
ICR1H
ICR1L
TIMSK