ATTIny2313-16MI ATMEL Corporation, ATTIny2313-16MI Datasheet - Page 78
ATTIny2313-16MI
Manufacturer Part Number
ATTIny2313-16MI
Description
8-bit AVR Microcontroller with 2K Bytes In-System Programmable Flash
Manufacturer
ATMEL Corporation
Datasheet
1.ATTINY2313-16MI.pdf
(211 pages)
- Current page: 78 of 211
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Timer/Counter Register –
TCNT0
Output Compare Register A –
OCR0A
Output Compare Register B –
OCR0B
78
ATtiny2313/V
Table 42. Clock Select Bit Description
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will
clock the counter even if the pin is configured as an output. This feature allows software
control of the counting.
The Timer/Counter Register gives direct access, both for read and write operations, to
the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes)
the Compare Match on the following timer clock. Modifying the counter (TCNT0) while
the counter is running, introduces a risk of missing a Compare Match between TCNT0
and the OCR0x Registers.
The Output Compare Register A contains an 8-bit value that is continuously compared
with the counter value (TCNT0). A match can be used to generate an Output Compare
interrupt, or to generate a waveform output on the OC0A pin.
The Output Compare Register B contains an 8-bit value that is continuously compared
with the counter value (TCNT0). A match can be used to generate an Output Compare
interrupt, or to generate a waveform output on the OC0B pin.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
CS02
0
0
0
0
1
1
1
1
CS01
0
0
1
1
0
0
1
1
R/W
R/W
R/W
7
0
7
0
7
0
CS00
0
1
0
1
0
1
0
1
R/W
R/W
R/W
6
0
6
0
6
0
Description
No clock source (Timer/Counter stopped)
clk
clk
clk
clk
clk
External clock source on T0 pin. Clock on falling edge.
External clock source on T0 pin. Clock on rising edge.
I/O
I/O
I/O
I/O
I/O
/(No prescaling)
/8 (From prescaler)
/64 (From prescaler)
/256 (From prescaler)
/1024 (From prescaler)
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
R/W
4
0
4
0
4
0
OCR0A[7:0]
OCR0B[7:0]
TCNT0[7:0]
R/W
R/W
R/W
3
0
3
0
3
0
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
0
1
0
1
0
R/W
R/W
R/W
0
0
0
0
0
0
2543C–AVR–12/03
OCR0A
OCR0B
TCNT0
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