ispPAC-CLK55xx Lattice Semiconductor, ispPAC-CLK55xx Datasheet - Page 23

• Manufacturer Part Number: ispPAC-CLK55xx
• Description: In-System Programmable Clock Generator with Universal Fan-Out Buffer
• Manufacturer: Lattice Semiconductor

Lattice Semiconductor
loads and to the ≈20Ω setting for driving HSTL. The far end of the transmission line must be terminated to an
appropriate VTT voltage through a 50Ω resistor.
Figure 20. Configuration for SSTL2, SSTL3, and HSTL Output Modes
When driving differential SSTL or HSTL loads, the above configuration should be duplicated on the ‘-’ output line of
the differential pair.
Figure 21 shows a typical configuration for the ispClock5500’s output driver when configured to drive LVDS or dif-
ferential LVPECL loads. The ispClock5500’s output impedance is disengaged when the driver is set to LVDS or
LVPECL mode. The far end of the transmission line must be terminated with a 100Ω resistor across the two signal
lines.
Figure 21. Configuration for LVDS and LVPECL Output Modes
Note that when in LVPECL output mode, the ispClock5500’s output driver provides an internal pull-down, unlike a
typical bipolar LVPECL driver. For this reason no external pull-down resistors are necessary and the driver may be
terminated with a single 100Ω resistor across the signal lines. For proper operation, pull-down resistors should
NOT be used with the ispClock5500’s LVPECL output mode.
Thermal Management
In applications where a majority of the ispClock5510 or ispClock5520’s outputs are active and operating at or near
maximum output frequency (320 MHz), package thermal limitations may need to be considered to ensure a suc-
cessful design. Thermal characteristics of the packages employed by Lattice Semiconductor may be found in the
document Thermal Management which may be obtained at www.latticesemi.com.
The maximum current consumption of the digital and analog core circuitry is approximately 157mA worst case
(I
MHz, both outputs in each bank enabled). This results in a total device dissipation:
CCD
+ I
CCA
), and each of the output banks may draw up to 35mA worst case (LVCMOS 3.3V, CL=18pF, f
LVDS/LVPECL
SSTL/HSTL
mode
Mode
ispClock5500
Ro : 40Ω (SSTL)
ispClock5500
≈20Ω (HSTL)
P
DMAX
= 3.3V x (10 x 35mA + 157mA) = 1.67W
23
Zo=50
Zo=50
Zo=50
ispClock5500 Family Data Sheet
VREF
RT=50
RT=100
VTT
SSTL/HSTL
Receiver
LVDS/PECL
Receiver
OUT
=320
(3)