AM79C972BKCW Advanced Micro Devices, AM79C972BKCW Datasheet - Page 106

• Manufacturer Part Number: AM79C972BKCW
• Description: PCnet-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
• Manufacturer: Advanced Micro Devices

Control and Status Registers
The CSR space is accessible by performing accesses
to the RDP (Register Data Port). The particular CSR
that is read or written during an RDP access will depend
upon the current setting of the RAP. RAP serves as a
pointer into the CSR space.
CSR0: Am79C972 Controller Status and Control
Register
Certain bits in CSR0 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR0 and write back
the value just read to clear the interrupt condition.
Bit
31-16
15
14
13
106
Name
RES
ERR
RES
CERR
Am79C972 control registers. A
read access will yield undefined
values.
Read/Write accessible always.
RAP is cleared by H_RESET or
S_RESET and is unaffected by
setting the STOP bit.
Read accessible always. ERR is
read only. Write operations are
ignored.
Description
Reserved locations. Written as
zeros and read as undefined.
Error is set by the OR of CERR,
MISS, and MERR. ERR remains
set as long as any of the error
flags are true.
Reserved locations. Read/Write
accessible always. Read returns
zero.
Collision Error is set by the
Am79C972 controller when the
device operates in half-duplex
mode and the collision inputs to
the GPSI port failed to activate
within 20 network bit times after
the chip terminated transmission
(SQE Test). This feature is a
transceiver test feature. CERR
reporting is disabled when the
GPSI port is active and the
Am79C972 controller operates in
full-duplex mode.
Am79C972
12
11
MISS
MERR
When the MII port is selected,
CERR is only reported when the
external PHY is operating as a
half-duplex 10BASE-T PHY.
CERR assertion will not result in
an interrupt being generated.
CERR assertion will set the ERR
bit.
Read/Write accessible always.
CERR is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
H_RESET, S_RESET, or by set-
ting the STOP bit.
Am79C972 controller when it has
lost an incoming receive frame
resulting from a Receive Descrip-
tor not being available. This bit is
the only immediate indication that
receive data has been lost since
there is no current receive de-
scriptor.
Counter (CSR112) also incre-
ments each time a receive frame
is missed.
When MISS is set, INTA is as-
serted if IENA is 1 and the mask
bit MISSM (CSR3, bit 12) is 0.
MISS assertion will set the ERR
bit, regardless of the settings of
IENA and MISSM.
Read/Write accessible always.
MISS is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
H_RESET, S_RESET, or by set-
ting the STOP bit.
Am79C972 controller when it re-
quests the use of the system in-
terface bus by asserting REQ
and has not received GNT asser-
tion after a programmable length
of time. The length of time in mi-
croseconds before MERR is as-
serted will depend upon the
setting of the Bus Timeout Regis-
ter (CSR100). The default setting
of CSR100 will give a MERR after
153.6
Missed Frame is set by the
Memory Error is set by the
CERR
MISS
s of bus latency.
The
is
is
Missed
cleared
cleared
Frame
by
by