AM79C972BKCW Advanced Micro Devices, AM79C972BKCW Datasheet - Page 93

• Manufacturer Part Number: AM79C972BKCW
• Description: PCnet-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
• Manufacturer: Advanced Micro Devices

order for the receiver to accept unicast frames directed
to this station.
The six bytes of the IEEE station address occupy the
first six locations of the Address PROM space. The
next six bytes are reserved. Bytes 12 and 13 should
match the value of the checksum of bytes 1 through 11
and 14 and 15. Bytes 14 and 15 should each be ASCII
“W” (57h). The above requirements must be met in
order to be compatible with AMD driver software.
APROMWE bit (BCR2, bit 8) must be set to 1 to enable
write access to the Address PROM space.
Reset Register
A read of the Reset register creates an internal soft-
ware reset (S_RESET) pulse in the Am79C972 control-
ler. The internal S_RESET pulse that is generated by
this access is different from both the assertion of the
hardware RST pin (H_RESET) and from the assertion
of the software STOP bit. Specifically, S_RESET is the
equivalent of the assertion of the RST pin (H_RESET)
except that S_RESET has no effect on the BCR or PCI
Configuration space locations.
The NE2100 LANCE-based family of Ethernet cards
requires that a write access to the Reset register fol-
lows each read access to the Reset register. The
Am79C972 controller does not have a similar require-
ment. The write access is not required and does not
have any effect.
Note: The Am79C972 controller cannot service any
slave accesses for a very short time after a read access
of the Reset register, because the internal S_RESET
operation takes about 1 s to finish. The Am79C972
controller will terminate all slave accesses with the as-
sertion of DEVSEL and STOP while TRDY is not as-
serted, signaling to the initiator to disconnect and retry
the access at a later time.
Word I/O Mode
After H_RESET, the Am79C972 controller is pro-
grammed to operate in Word I/O mode. DWIO (BCR18,
bit 7) will be cleared to 0. Table 17 shows how the 32
bytes of address space are used in Word I/O mode.
All I/O resources must be accessed in word quantities
and on word addresses. The Address PROM locations
can also be read in byte quantities. The only allowed
DWord operation is a write access to the RDP, which
switches the device to DWord I/O mode. A read access
other than listed in the table below will yield undefined
data, a write operation may cause unexpected repro-
Am79C972
gramming of the Am79C972 control registers. Table 18
shows legal I/O accesses in Word I/O mode.
Double Word I/O Mode
The Am79C972 controller can be configured to operate
in DWord (32-bit) I/O mode. The software can invoke
the DWIO mode by performing a DWord write access
to the I/O location at offset 10h (RDP). The data of the
write access must be such that it does not affect the in-
tended operation of the Am79C972 controller. Setting
the device into 32-bit I/O mode is usually the first oper-
ation after H_RESET or S_RESET. The RAP register
will point to CSR0 at that time. Writing a value of 0 to
CSR0 is a safe operation. DWIO (BCR18, bit 7) will be
set to 1 as an indication that the Am79C972 controller
operates in 32-bit I/O mode.
Note: Even though the I/O resource mapping changes
when the I/O mode setting changes, the RDP location
offset is the same for both modes. Once the DWIO bit
has been set to 1, only H_RESET can clear it to 0. The
DWIO mode setting is unaffected by S_RESET or set-
ting of the STOP bit. Table 19 shows how the 32 bytes
of address space are used in DWord I/O mode.
All I/O resources must be accessed in DWord quanti-
ties and on DWord addresses. A read access other
than listed in Table 20 will yield undefined data, a write
operation may cause unexpected reprogramming of
the Am79C972 control registers.
Table 17. I/O Map In Word I/O Mode (DWIO = 0)
00h - 0Fh
18h - 1Fh
Offset
10h
12h
14h
16h
No. of
Bytes
16
2
2
2
2
8
RAP (shared by RDP and BDP)
Reset Register
Reserved
Register
APROM
RDP
BDP
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