AM79C972BKCW Advanced Micro Devices, AM79C972BKCW Datasheet - Page 115

• Manufacturer Part Number: AM79C972BKCW
• Description: PCnet-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
• Manufacturer: Advanced Micro Devices

3
2
1
0
MPINTE
MPEN
MPMODE
SPND
Read/Write accessible always.
MPINT is cleared by the host by
writing a 1. Writing a 0 has no af-
fect.
H_RESET, S_RESET, or by set-
ting the STOP bit.
Read/Write accessible always.
MPINT is cleared to 0 by
H_RESET or S_RESET and is
not affected by setting the STOP
bit.
Read/Write accessible always.
MPEN
H_RESET or S_RESET and is
not affected by setting the STOP
bit.
Read/Write accessible always.
MPMODE is cleared to 0 by
H_RESET or S_RESET and is
not affected by setting the STOP
bit
mode and the Am79C972 con-
troller receives a Magic Packet
frame. When MPINT is set to 1,
INTA is asserted if IENA (CSR0,
bit 6) and the enable bit MPINTE
are set to 1.
Magic Packet Interrupt Enable. If
MPINTE is set to 1, the MPINT bit
will be able to set the INTR bit.
Magic Packet Enable. MPEN al-
lows activation of the Magic
Packet mode by the host. The
Am79C972 controller will enter
the Magic Packet mode when
both MPEN and MPMODE are
set to 1.
The Am79C972 controller will en-
ter the Magic Packet mode when
MPMODE is set to 1 and either
PG is asserted or MPEN is set to
1.
Suspend. Setting SPND to 1 will
cause the Am79C972 controller
to start requesting entrance into
suspend mode. The host must
poll SPND until it reads back 1 to
determine that the Am79C972
controller has entered the sus-
pend mode. Setting SPND to 0
will get the Am79C972 controller
MPINT
is
cleared
is
cleared
to
0
Am79C972
by
by
CSR6: RX/TX Descriptor Table Length
Bit
31-16 RES
15-12 TLEN
Name
out of suspend mode. SPND can
only be set to 1 if STOP (CSR0,
bit 2) is set to 0. H_RESET,
S_RESET or setting the STOP bit
will get the Am79C972 controller
out of suspend mode.
Requesting entrance into the
suspend mode by the host de-
pends on the setting of the
FASTSPNDE bit (CSR7, bit 15).
Refer to the bit description of the
FASTSPNDE bit and the Sus-
pend section in Detailed Func-
tions, Buffer Management Unit
for details.
In suspend mode, all of the CSR
and BCR registers are accessi-
ble. As long as the Am79C972
controller is not reset while in
suspend mode (by H_RESET,
S_RESET or by setting the STOP
bit), no re-initialization of the de-
vice is required after the device
comes out of suspend mode. The
Am79C972 controller will contin-
ue at the transmit and receive de-
scriptor
where it had left, when it entered
the suspend mode.
Read/Write accessible always.
SPND is cleared by H_RESET,
S_RESET, or by setting the
STOP bit.
zeros and read as undefined.
encoded ring length (TLEN) field
read from the initialization block
during the Am79C972 controller
initialization. This field is written
during the Am79C972 controller
initialization routine.
Read accessible only when either
the STOP or the SPND bit is set.
Write operations have no effect
and should not be performed.
TLEN is only defined after initial-
ization. These bits are unaffected
Description
Reserved locations. Written as
Contains a copy of the transmit
ring
locations,
from
115