AM79C973KCW Advanced Micro Devices, AM79C973KCW Datasheet - Page 125

• Manufacturer Part Number: AM79C973KCW
• Description: PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
• Manufacturer: Advanced Micro Devices

6
5
4
3
IENA
RXON
TXON
TDMD
or SLPINT, INTA will be active in-
dependent of the state of INEA.
Read accessible always. INTR is
read only. INTR is cleared by
clearing all of the active individual
interrupt bits that have not been
masked out.
be active if the Interrupt Flag is
set. If IENA = 0, then INTA will be
disabled regardless of the state
of INTR.
Read/Write accessible always.
IENA is set by writing a 1 and
cleared by writing a 0. IENA is
cleared
S_RESET and setting the STOP
bit.
ceive function is enabled. RXON
is set if DRX (CSR15, bit 0) is set
to 0 after the START bit is set. If
INIT and START are set together,
RXON will not be set until after
the initialization block has been
read in.
Read accessible always. RXON
is read only. RXON is cleared by
H_RESET or S_RESET and set-
ting the STOP bit.
transmit function is enabled.
TXON is set if DTX (CSR15, bit 1)
is set to 0 after the START bit is
set. If INIT and START are set to-
gether, TXON will not be set until
after the initialization block has
been read in.
This bit will reset if the DXSUFLO
bit (CSR3, bit 6) is reset and there
is an underflow condition encoun-
tered.
Read accessible always. TXON
is read only. TXON is cleared by
H_RESET or S_RESET and set-
ting the STOP bit.
causes the Buffer Management
Unit to access the Transmit De-
scriptor Ring without waiting for
Interrupt Enable allows INTA to
Receive On indicates that the re-
Transmit On indicates that the
Transmit Demand, when set,
by
H_RESET
P R E L I M I N A R Y
Am79C973/Am79C975
or
2
1
0
STOP
STRT
INIT
TDMD is required to be set if the
TXDPOLL bit in CSR4 is set. Set-
ting TDMD while TXDPOLL = 0
merely hastens the Am79C973/
Am79C975 controller’s response
to a Transmit Descriptor Ring En-
try.
Read/Write accessible always.
TDMD is set by writing a 1. Writ-
ing a 0 has no effect. TDMD will
be cleared by the Buffer Manage-
ment Unit when it fetches a
Transmit Descriptor. TDMD is
cleared
S_RESET and setting the STOP
bit.
Read/Write accessible always.
STOP is set by writing a 1, by
H_RESET or S_RESET. Writing
a 0 has no effect. STOP is
cleared by setting either STRT or
INIT.
Read/Write accessible always.
STRT is set by writing a 1. Writing
a 0 has no effect. STRT is cleared
by H_RESET, S_RESET, or by
setting the STOP bit.
the poll-time counter to elapse. If
TXON is not enabled, TDMD bit
will be reset and no Transmit De-
scriptor Ring access will occur.
STOP assertion disables the chip
from all DMA activity. The chip re-
mains inactive until either STRT
or INIT are set. If STOP, STRT
and INIT are all set together,
STOP will override STRT and
INIT.
STRT
Am79C973/Am79C975 controller
to send and receive frames, and
perform buffer management op-
erations. Setting STRT clears the
STOP bit. If STRT and INIT are
set together, the Am79C973/
Am79C975 controller initializa-
tion will be performed first.
INIT
Am79C973/Am79C975 controller
to begin the initialization proce-
dure which reads in the initializa-
tion block from memory. Setting
assertion
by
assertion
H_RESET
enables
enables
125
the
or