AM79C973KCW Advanced Micro Devices, AM79C973KCW Datasheet - Page 84

• Manufacturer Part Number: AM79C973KCW
• Description: PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
• Manufacturer: Advanced Micro Devices

Scrambler/Descrambler
The 4B/5B encoded data has repetitive patterns which
result in peaks in the RF spectrum large enough to
keep the system from meeting the standards set by
regulatory agencies such as the FCC. The peaks in the
radiated signal are reduced significantly by scrambling
the transmitted signal. Scramblers add the output of a
random generator to the data signal. The resulting sig-
nal has fewer repetitive data patterns.
After reset, the scrambler seed will be set to the PHY
address value to help improve the EMI performance of
the device.
The scrambled data stream is descrambled, at the re-
ceiver, by adding it to the output of another random
generator. The receiver’s random generator has the
same function as the transmitter’s random generator.
Link Monitor
The Link Monitor process is responsible for determin-
ing whether the underlying receive channel is providing
reliable data. This process takes advantage of the con-
tinuous indication of signal detect by the PMD (PDX &
MLT-3). The process sets the link_status to FAIL when-
ever signal_status is OFF. The link is reliable whenever
the signal_status has been continuously ON for 330 -
1000 ms. The implementation is in compliance with
Clause 24 of the IEEE 802.3u specification.
The 10BASE-T Link Monitor monitors the line for link
pulses, while the 100BASE-T Link Monitor expects 100
Mbps idle signals. When the Link Monitor detects both
10 Mbps and 100 Mbps signals, a state called Parallel
Fault is entered, where the Link Monitor simply halts
and fails to report a link. This condition can be caused
by spurious noise on the network line. Consult the IEEE
802.3u specification for more information. The Parallel
Fault Detect condition is displayed in Register 6, bit 4.
The current link status of this port is displayed In the
PHY Management Status Register (Register 1, bit 2).
Far End Fault Generation and Detection
Far End Fault Generation and Detection is imple-
mented in the 10/100 PHY for 100BASE-TX over STP
and 100BASE-FX. This block generates a special Far
End Fault indication to its far end peer. This indication
is generated only when an error condition is detected
on the receive channel. When Far End Fault Indication
is detected from the far end peer, this block will cause
the link monitor to transition the link_status to FAIL.
This action in-turn will cause IDLE code-group bits to
be automatically transmitted. This is necessary to re-
establish communication when the link is repaired. The
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P R E L I M I N A R Y
Am79C973/Am79C975
implementation is in compliance with the Clause 24 of
IEEE 802.3u specification.
Far End Fault Indication can be initialized using the
PHY Control/Status Register (ANR17, bit 10).
MLT-3 and Adaptive Equalization
This block is responsible for converting the NRZI data
stream from the PDX block to a currently sourced
MLT-3 encoded data stream. The effect of MLT-3 is the
reduction of energy on the media (TX cable) in the crit-
ical frequency range of 20 MHz to 100 MHz. The re-
ceive section of this block is responsible for equalizing
and amplifying the received data stream and link detec-
tion. The adaptive equalizer compensates for the am-
plitude and phase distortion due to the cable.
MLT-3 is a tri-level signal. All transitions are between
0 V and +1 V or 0 V and -1 V. A transition has a logical
value of 1 and a lack of a transition has a logical value
of 0. The benefit of MLT-3 is that it reduces the maxi-
mum frequency over the data line. The bit rate of TX
data is 125 Mbps. The maximum frequency (using
NRZI) is half of 62.5 MHz. MLT-3 reduces the maximum
frequency to 31.25 MHz.
The implementation of this block is in compliance with
ANSI X3712 TP-PMD/312, Revision 2.1 that defines a
125-Mbps, full-duplex signalling for twisted pair wiring.
A data signal stream following MLT-3 rules is illustrated
in Figure 36. The data stream is 1010101.
The TX± drivers convert the NRZI serial output to
MLT-3 format. The RX± receivers convert the received
MLT-3 signals to NRZI. When the TX port of the 10/100
PHY is connected as in Figure 37, the transmit and re-
ceive signals will be compliant with IEEE 802.3u Sec-
tion 25. The required signals (MLT-3) are described in
detail in ANSI X3.263:1995 TP-PMD Revision 2.2
(1995).
The 10/100 PHY provides on-chip filtering. External fil-
ters are not required for either the transmit or receive
signals.