AM79C973KCW Advanced Micro Devices, AM79C973KCW Datasheet - Page 162

• Manufacturer Part Number: AM79C973KCW
• Description: PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
• Manufacturer: Advanced Micro Devices

BCR2: Miscellaneous Configuration
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16 RES
15
14
13
162
53
54
SMIUEN
DISSCR_SFEX
PHYSELEN This
Name
M_IP_ADR[15:0]
M_IPADR[31:16]
Reserved locations. Written as
zeros and read as undefined.
(For Am79C975 only) SMIUEN is
used to enable/disable the Serial
Management Interface Unit in the
Am79C975 controller.
If SMIUEN is set to 0 (default),
the SMIU is disable. If SMIUEN is
set to 1, the SMIU is enabled.
Read/Write accessible always.
SMIUEN is cleared to 0 by
H_RESET and is unaffected by
S_RESET or by setting the STOP
bit.
This bit is used to disable the
scrambler/descrambler when the
device is used in PECL mode.
This bit defaults to 0, which en-
ables the scrambler/descrambler
for MLT3 applications.
When DISSCR_SFEX is set to 1,
the scrambler will be disabled for
fiber applications.
Read/Write accessible always.
This bit is cleared to 0 by
H_RESET and is unaffected by
S_RESET or by setting the STOP
bit.
BCR18[4:3] for software selec-
tion of various operation and test
modes. When PHYSELEN is set
to 0 (default), the two bits can
only be written from the EE-
PROM. When PHYSELEN is set
to 1, writes to BCR18[4:3] are en-
abled.
Description
bit
enables
0000h
0000h
Table 30. BCR Registers (Am79C975)
P R E L I M I N A R Y
writes
Management IP Address [15:0]
Management IP Address [31:16]
Am79C973/Am79C975
to
12
11
10
9
LEDPE
RESET_SFEX
I2C_M3
I2C_M2
(Am79C975 only). This bit is used
(Am79C975 only). This bit is used
Read/Write accessible always.
PHYSELEN is cleared to 0 by
H_RESET and is unaffected by
S_RESET or by setting the STOP
bit.
LED Program Enable. When
LEDPE is set to 1, programming
of the LED0 (BCR4), LED1
(BCR5),
LED3 (BCR7) registers is en-
abled. When LEDPE is cleared to
0, programming of LED0 (BCR4),
LED1 (BCR5), LED2 (BCR6),
and LED3 (BCR7) registers is
disabled. Writes to those regis-
ters will be ignored.
Read/Write accessible always.
LEDPE is cleared to 0 by
H_RESET and is unaffected by
S_RESET or by setting the STOP
bit.
This bit is used to reset the inter-
nal PHY. When RESET_SFEX is
set to 1, the internal PHY will stay
reset
cleared to 0.
Read/Write accessible always.
RESET_SFEX is cleared to 0 by
H_RESET and is unaffected by
S_RESET or by setting the STOP
bit.
to set the operating frequency of
the SMIU core. It represents the
value in the D6 bit position (see
Appendix B on SMIU Bus Fre-
quency.
Read/Write accessible always.
I2C_M3 is cleared by H_RESET
and is unaffected by S_RESET or
by setting the STOP bit.
to set the operating frequency of
the SMIU core. It represents the
until
Yes
Yes
LED2
RESET_SFEX
(BCR6),
Yes
Yes
and
is