WS57C45 STMicroelectronics, WS57C45 Datasheet - Page 6

• Manufacturer Part Number: WS57C45
• Description: HIGH-SPEED 2K x 8 REGISTERED CMOS PROM/RPROM
• Manufacturer: STMicroelectronics

WS57C45
Synchronous Enable Programming
The WS57C45 contains both a synchronous and asynchronous enable feature. The part is delivered configured in
the asynchronous mode and only requires alteration if the synchronous mode is required. This is accomplished by
programming an on-chip EPROM cell. Similar to the Initial Byte, this function is enabled and addressed by using a
super voltage. Referring to the Mode Selection table, V
procedure addresses the EPROM cell that programs the synchronous enable feature. The EPROM cell is
programmed with a 10 ms program pulse on CP/PGM. It does not require any data since there is no selection as to
how synchronous enable may be programmed, only if it is to be programmed.
Synchronous Enable Verification
The WS57C45’s synchronous enable function is verified operationally. Apply power for read operation with OE/OE
and INIT/V
impedance state. Next take OE/OE
(CP/PGM) from V
should remain driven. Clocking CP/PGM once more from V
impedance state.
Blank Check
Upon delivery from WaferScale Integration, Inc. or after each erasure (see Erasure section), the WS57C45 has all
2048 bytes in the ‘0’ state. “1’s” are loaded into the WS57C45 through the procedure of programming.
NOTES: 5. X = Don’t Care but not to exceed V
2-26
MODE
Read (Note 6)
Output Disable
Program (Notes 5 & 7)
Program Verify (Notes 5 & 7)
Program Inhibit (Notes 5 & 7)
Intelligent Program (Notes 5 & 7)
Program Synch Enable (Note 7)
Program Initial Byte (Note 7)
Initial Byte Read
6. During read operation, the output latches are loaded on a “0” to “1” transition of CP.
7. During programming and verification, all unspecified pins to be at V
PP
READ OR OUTPUT DISABLE
at V
IL
IH
to V
and take the clock (CP/PGM) from V
IH
and the outputs will now contain the data that is present. Take OE/OE
S
to V
PP
IL
.
. The outputs will remain in the high impedance state. Take the clock
V
V
A
X
X
X
X
X
X
X
IH
IL
2
CP/PGM
PP
IL
V
V
V
V
V
V
is applied to A
X
X
X
to V
IL
IH
IH
IL
IL
IL
IL
to V
IH
IL .
. The output data bus should be in a high
IH
(OE/OE
PIN FUNCTION
should place the outputs again in a high
V
V
V
V
V
V
1
V
V
V
IH
IH
IH
IH
IH
IH
IL
IL
IL
followed by V
S
)/VFY
INIT/V
V
V
V
V
V
V
IH
V
V
V
PP
PP
PP
PP
PP
PP
IH
IH
IL
applied to A
PP
S
V
V
to V
A
X
X
X
X
X
X
X
PP
PP
1
2
IH
. This
. The output
OUTPUTS
Data Out
Data Out
Data Out
Data In
Data In
Data In
High Z
High Z
High Z
S