K4R881869 Samsung semiconductor, K4R881869 Datasheet - Page 15

• Manufacturer Part Number: K4R881869
• Description: 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
• Manufacturer: Samsung semiconductor

K4R881869M
ROW-to-ROW Interaction - contin-
ued
Cases RR13 through RR16 summarize the combinations of
two successive PRER commands. In case RR13 there is no
restriction since two devices are addressed. In RR14, t
applies, since the same device is addressed. In RR15 and
RR16, the same bank or an adjacent bank may be given
repeated PRER commands with only the t
Two adjacent banks can’t be activate simultaneously. A
precharge command to one bank will thus affect the state of
the adjacent banks (and sense amps). If bank Ba is activate
and a PRER is directed to Ba, then bank Ba will be
precharged along with sense amps Ba-1/Ba and Ba/Ba+1. If
bank Ba+1 is activate and a PRER is directed to Ba, then
bank Ba+1 will be precharged along with sense amps
Ba/Ba+1 and Ba+1/Ba+2. If bank Ba-1 is activate and a
PRER is directed to Ba, then bank Ba-1 will be precharged
along with sense amps Ba/Ba-1 and Ba-1/Ba-2.
A ROW packet may contain commands other than ACT or
PRER. The REFA and REFP commands are equivalent to
ACT and PRER for interaction analysis purposes. The inter-
action rules of the NAPR, NAPRC, PDNR, RLXR, ATTN,
TCAL, and TCEN commands are discussed in later sections
(see Table 7 for cross-ref).
ROW-to-COL Packet Interaction
Figure 7 shows two packets on the ROW and COL pins.
They must be separated by an interval t
depends upon the packet contents. Table 11 summarizes the
t
packet is earlier than the ROW packet, it is considered a
COL-to-ROW packet interaction.
RCDELAY
Case #
RC1
RC2
RC3
RC4
RC5
RC6
RC7
RC8
RC9
ROPa
ACT
ACT
ACT
ACT
ACT
PRER
PRER
PRER
PRER
values for all possible cases. Note that if the COL
Da
Da
Da
Da
Da
Da
Da
Da
Da
Da
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Table 11: ROW-to-COL Packet Interaction - Rules
COPb
NOCOP,RD,retire
NOCOP
RD,retire
RD,retire
RD,retire
NOCOP,RD,retire
NOCOP
RD,retire
RD,retire
RCDELAY
PP
restriction.
which
PP
Page 13
Db
/= Da
== Da
== Da
== Da
== Da
/= Da
== Da
== Da
== Da
Cases RC1 through RC5 summarize the rules when the
ROW packet has an ACT command. Figure 15 and
Figure 16 show examples of RC5 - an activation followed by
a read or write. RC4 is an illegal situation, since a read or
write of a precharged banks is being attempted (remember
that for a bank to be activated, adjacent banks must be
precharged). In cases RC1, RC2, and RC3, there is no inter-
action of the ROW and COL packets.
Cases RC6 through RC8 summarize the rules when the
ROW packet has a PRER command. There is either no inter-
action (RC6 through RC9) or an illegal situation with a read
or write of a precharged bank (RC9).
The COL pins can also schedule a precharge operation with
a RDA, WRA, or PREC command in a COLC packet or a
PREX command in a COLX packet. The constraints of these
precharge operations may be converted to equivalent PRER
command constraints using the rules summarized in
Figure 14.
CTM/CFM
COL4
ROW2
DQA8..0
DQB8..0
..COL0
Figure 7: ROW-to-COL Packet Interaction- Timing
..ROW0
Bb
xxxx
xxxx
/= {Ba,Ba+1,Ba-1}
== {Ba+1,Ba-1}
== Ba
xxxx
xxxx
/= {Ba,Ba+1,Ba-1}
== {Ba+1,Ba-1}
T
0
ROPa a0
Transaction a: ROPa
Transaction b: COPb
T
1
T
2
T
3
T
4
T
Cb1 t
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
5
T
6
Preliminary
Direct RDRAM
T
Rev. 0.9 Jan. 2000
7
0
0
0
Illegal
t
0
0
0
Illegal
RCD
RCDELAY
T
8
T
COPb b1
9
T
10
b1= {Db,Bb,Cb1}
a0 = {Da,Ba,Ra}
T
11
T
12
T
13
T
t
14
RCDELAY
T
15
Example
Figure 15
T
16
T
17
T
18
T
™
19
T