K4R881869 Samsung semiconductor, K4R881869 Datasheet - Page 47

• Manufacturer Part Number: K4R881869
• Description: 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
• Manufacturer: Samsung semiconductor

K4R881869M
a. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0.
b. This parameter also applies to a -800 or -711 part when operated with t
c. This parameter also applies to a -800 part when operated with t
d. t
e. With V
f. Effective hold becomes t
if [PDNX•256•t
Symbol
t
t
t
t
t
t
t
t
t
t
t
v
v
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DR2,
CYCLE1
CH1
S1
H1
S2
H2
S3
H3
S4
H4
NPQ
READTOCC
CCSAMTOREAD
CE
CD
FRM
NLIMIT
REF
CCTRL
TEMP
TCEN
TCAL
TCQUIET
PAUSE
IL,CMOS
IH,CMOS
S,MIN
, t
t
DF2
CL1
and t
IL,CMOS
H,MIN
SCYCLE
=0.5V
for other t
] < [PDNXA•64•t
CMOS
Parameter
CMD, SCK input rise and fall times
SCK cycle time - Serial control register transactions
SCK cycle time - Power transitions
SCK high and low times
CMD setup time to SCK rising or falling edge
CMD hold time to SCK rising or falling edge
SIO0 setup time to SCK falling edge
SIO0 hold time to SCK falling edge
PDEV setup time on DQA5..0 to SCK rising edge.
PDEV hold time on DQA5..0 to SCK rising edge.
ROW2..0, COL4..0 setup time for quiet window
ROW2..0, COL4..0 hold time for quiet window
CMOS input low voltage - over/undershoot voltage duration is less
than or equal to 5ns
CMOS input high voltage - over/undershoot voltage duration is
less than or equal to 5ns
Quiet on ROW/COL bits during NAP/PDN entry
Offset between read data and CC packets (same device)
Offset between CC packet and read data (same device)
CTM/CFM stable before NAP/PDN exit
CTM/CFM stable after NAP/PDN entry
ROW packet to COL packet ATTN framing delay
Maximum time in NAP mode
Refresh interval
Current control interval
Temperature control interval
TCE command to TCAL command
TCAL command to quiet window
Quiet window (no read data)
RDRAM delay (no RSL operations allowed)
H4
’=t
-0.4V and V
CYCLE
H4
+[PDNXA•64•t
values can be interpolated between or extrapolated from the timings at the 3 specified t
SCYCLE
IH,CMOS
+t
=0.5V
SCYCLE
PDNXB,MAX
CMOS
+t
Table 19: Timing Conditions
PDNXB,MAX
+0.4V
]. See Figure 48.
CYCLE
e
e
f
=2.81ns.
]-[PDNX•256•t
CYCLE
Page 45
=3.33ns.
SCYCLE
34 t
]
V
CMOS
+ 0.4
1000
Min
4.25
1.25
- 0.7
100
150
140
5.5
10
40
40
12
CYCLE
-1
1
0
5
4
8
2
7
2
-
/2
V
V
CMOS
100ms
CMOS
200.0
Max
10.0
100
2.0
0.4
0.7
32
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
/2 -
+
Preliminary
Direct RDRAM
Rev. 0.9 Jan. 2000
CYCLE
ms/t
t
t
t
t
t
t
t
t
t
t
t
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
Unit
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CYCLE
V
V
s
s
values.
Figure 48,
Figure(s)
Figure 56
Figure 56
Figure 56
Figure 56
Figure 56
Figure 56
Figure 56
Figure 56
Figure 57
Figure 48
Figure 48
Figure 47
Figure 51
Figure 51
Figure 48
Figure 47
Figure 46
Figure 45
Figure 50
Figure 51
Figure 52
Figure 52
Figure 52
Figure 52
page 28
™