K4R881869D Samsung semiconductor, K4R881869D Datasheet
K4R881869D
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K4R881869D Summary of contents
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... K4R571669D/K4R881869D 256/288Mbit RDRAM 512K x 16/18bit x 32s banks Direct RDRAM Version 1.4 July 2002 Page -1 Direct RDRAM (D-die) TM Version 1.4 July 2002 ™ ...
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... K4R571669D/K4R881869D Change History Version 1.4( July 2002) - First Copy ( Version 1.4 is named to unify the version of component and device operation datasheets) - Based on the 256/288Mb A-die RDRAM Version 1.4 Page 0 ™ Direct RDRAM Version 1.4 July 2002 ...
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... WBGA package. c.“C” - RDRAM core uses normal power self refresh. Version 1.4 July 2002 Page 1 ™ 230 Part Number b c K4R571669D K4R571669D-FCN9 K4R571669D-FCM9 K4R571669D-FCM8 K4R571669D-FCK8 K4R881869D-FCT9 K4R881869D-FCN9 K4R881869D-FCM9 K4R881869D-FCM8 K4R881869D-FCK8 ...
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... K4R571669D/K4R881869D Pinouts and Definitions Center-Bonded Devices These tables shows the pin assignments of the center-bonded RDRAM package. The mechanical dimensions of this V GND GND V CMD DQA8 DQA7 DQA5 GND GND DQA6 DQA4 3 V GND SCK V DD CMOS ...
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... K4R571669D/K4R881869D Signal I/O Type a SIO1,SIO0 I/O CMOS a CMD I CMOS a SCK I CMOS DDa V CMOS GND GNDa b DQA8..DQA0 I/O RSL b CFM I RSL b CFMN I RSL V REF b CTMN I RSL b CTM I RSL b RQ7..RQ5 or I RSL ROW2..ROW0 b RQ4..RQ0 or I RSL COL4..COL0 b DQB8.. I/O RSL DQB0 Total pin count per package a. All CMOS signals are high-true ...
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... K4R571669D/K4R881869D RQ7..RQ5 or DQB8..DQB0 ROW2..ROW0 3 9 1:8 Demux Packet Decode ROWR ROWA ROP Match Mux DM Row Decode PRER ACT Sense Amp 64x72 Internal DQB Data Path Figure 2: 256/288-Mbit (512Kx16/18x32s) RDRAM Device Block Diagram ...
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... K4R571669D/K4R881869D General Description Figure block diagram of the 256/288-Mbit RDRAM device. It consists of two major blocks: a “core” block built from banks and sense amps similar to those found in other types of DRAM, and a Direct Rambus which permits an external controller to access this core ...
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... K4R571669D/K4R881869D Packet Format Figure 3 shows the formats of the ROWA and ROWR packets on the ROW pins. Table 3 describes the fields which comprise these packets. DR4T and DR4F bits are encoded to contain both the DR4 device address bit and a framing bit which allows the ROWA or ROWR packet to be recognized by the RDRAM device ...
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... K4R571669D/K4R881869D CTM/CFM ROW2 DR4T DR2 BR0 BR3 RsvR ROW1 DR4F DR1 BR1 BR4 RsvR ROW0 DR3 DR0 BR2 RsvB AV=1 ROWA Packet CTM/CFM DC4 S=1 COL4 DC3 COL3 DC2 COP1 COL2 DC1 COP0 COL1 DC0 COP2 COL0 COLC Packet ...
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... K4R571669D/K4R881869D Field Encoding Summary Table 5 shows how the six device address bits are decoded for the ROWA and ROWR packets. The DR4T and DR4F encoding merges a fifth device bit with a framing bit. When neither bit is asserted, the device is not selected. Note that a ...
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... K4R571669D/K4R881869D Table 7 shows the COP field encoding. The device must be in the ATTN power state in order to receive COLC packets. The COLC packet is used primarily to specify RD (read) and WR (write) commands. Retire operations (moving data from the write buffer to a sense amp) happen automatically. See Figure 18 for a more detailed description ...
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... K4R571669D/K4R881869D Electrical Conditions Symbol T Junction temperature under bias Supply voltage DD, DDA V V Supply voltage droop (DC) during NAP interval (t DD,N, DDA Supply voltage ripple (AC) during NAP interval (t DD,N, DDA Supply voltage for CMOS pins (2.5V controllers) CMOS Supply voltage for CMOS pins (1.8V controllers) ...
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... K4R571669D/K4R881869D Electrical Characteristics Symbol Θ Junction-to-Case thermal resistance current @ V REF REF REF,MAX I RSL output high current @ (0≤V OH RSL I current @ ALL RSL I current @ t OL ∆I RSL I current resolution step Dynamic output impedance @ V OUT I RSL I current @ V OL,NOM OL RSL I current @ V ...
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... K4R571669D/K4R881869D Timing Conditions Symbol CTM and CFM cycle times (-1066) t CYCLE CTM and CFM cycle times (-800) CTM and CFM input rise and fall times. Use the minimum value these parameters during testing CTM and CFM high and low times ...
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... K4R571669D/K4R881869D Symbol t CTM/CFM stable after NAP/PDN entry CD t ROW packet to COL packet ATTN framing delay FRM t Maximum time in NAP mode NLIMIT t Refresh interval REF Interval after PDN or NAP (with self-refresh) exit in which all t BURST banks of the RDRAM device must be refreshed at least once. ...
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... K4R571669D/K4R881869D Timing Characteristics Symbol CTM-to-DQA/DQB output time @ CTM-to-DQA/DQB output time @ t DQA/DQB output rise and fall times @ DQA/DQB output rise and fall times @ t t SCK(neg)-to-SIO0 delay @ SCK(pos)-to-SIO0 delay @ SIO rise/fall @ C QR1 QF1 ...
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... K4R571669D/K4R881869D Timing Parameters Parameter Description Row Cycle time of RDRAM banks -the interval between ROWA pack ets with ACT commands to the same bank. RAS-asserted time of RDRAM bank - the interval between ROWA t packet with ACT command and next ROWR packet with PRER RAS mand to the same bank ...
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... K4R571669D/K4R881869D Absolute Maximum Ratings Symbol V Voltage applied to any RSL or CMOS pin with respect to Gnd I,ABS Voltage on VDD and VDDA with respect to Gnd DD,ABS DDA,ABS T Storage temperature STORE T Minimum operation temperature MIN Θ Note*) Component : refer to T RIMM: refre ...
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... K4R571669D/K4R881869D Capacitance and Inductance Symbol Parameter and Conditions - RSL pins RSL effective input inductance L I RSL effective input inductance Mutual inductance between any DQA or DQB RSL signals Mutual inductance between any ROW or COL RSL signals. ∆L Difference in L value between any RSL pins of a single device. ...
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... K4R571669D/K4R881869D Center-Bonded WBGA Package (92balls) Figure 4 shows the form and dimensions of the recom- mended package for the 92balls center-bonded WBGA device class Figure 4: Center-Bonded WBGA Package Table lists the numerical values corresponding to dimen- sions shown in Figure 4 ...